LibreSilicon - User contributions [en]

LibrePDK Padframe SPICE Verification Report GF180A@3.3V

2026-09-01T16:40:39Z

Leviathan: /* 4. Full Dynamic Loopback */

= LibrePDK Padframe SPICE Verification Report =

'''Technology:''' IHP SG13G2 (130nm BiCMOS)
'''Operating Voltage:''' 3.3 V
'''Verification Date:''' 2026-09-01 16:01:45 UTC
'''Extracted Netlist:''' <code>padframe.spice</code> (Magic VLSI Hierarchical Extraction)

== Executive Summary ==
{| class="wikitable" style="text-align:center; width:90%;"
! Test Scenario !! Target Net / Pad !! Measured Values !! Design Specification !! Status
|-
| style="text-align:left;" | '''ESD Clamping Transient''' || PAD_GPIO_0 (ESD Clamps) || Peak Clamped: 4.30 V || < 15.0 V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Output Drive (Write)''' || gpio_out_0 → PAD_GPIO_0 || Low: 2.84 V, High: 0.65 V || Rail-to-rail driver transition || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Input Sensing (Read / Hi-Z)''' || PAD_GPIO_1 → gpio_in_1 || Pad 0V → 0.00 V, Pad 3.3V → 2.87 V || Pad 0V -> Core > 0.8V, Pad 3.3V -> Core < 0.2V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Pad-to-Pad Dynamic Loopback''' || PAD_GPIO_0 → PAD_GPIO_1 || Bus: 1.40V / 1.37V | Rx: 2.85V / -0.01V || Full rail-to-rail dynamic loopback across frame || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|}

== Core Signal & Bonding Pad Interface Mapping ==
The LibrePDK padframe generator exposed unique net names defined in the JSON configuration for seamless Coriolis LEF/DEF digital core integration:

{| class="wikitable" style="width:90%; font-family:monospace;"
! Subcircuit Port Name !! Direction !! Interface Type !! Associated Physical Layer
|-
| '''VDD''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''VSS''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''gpio_in_0''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_0''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_0''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_0''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''gpio_in_1''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_1''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_1''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_1''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_miso_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_miso_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_miso_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MISO''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_cs_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_cs_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_cs_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_CS''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_tx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_tx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_tx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_TX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_rx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_rx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_rx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_RX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_sclk_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_sclk_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_sclk_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_SCLK''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_mosi_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_mosi_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_mosi_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MOSI''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|}

== Transient Simulation Waveforms ==

=== 1. ESD Clamping Event ===
Transient simulation applying a 2kV / 1.33A peak Human Body Model (HBM) current pulse directly to the bonding pad:
[[File:Sim 1 esd clamping GF180A@3.3V.png|thumb|center|700px|ESD Diode and Rail Clamping Response under 1.33A Transient Current Pulse]]

=== 2. Digital Output Drive (Write) ===
Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:
[[File:Sim 2 signal write GF180A@3.3V.png|thumb|center|700px|Signal Write: Core OUT driving Bonding Pad (0V to 3.3V)]]

=== 3. Digital Input Sensing (Read / Hi-Z) ===
External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:
[[File:Sim 3 signal read hiz GF180A@3.3V.png|thumb|center|700px|Signal Read: External Bonding Pad voltage sensed at Core IN]]

=== 4. Full Dynamic Loopback ===
End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):
[[File:Sim 4 pad to pad loopback GF180A@3.3V.png|thumb|center|700px|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]

== Physical Verification & GDS Delivery ==
* '''GDSII Top Level:''' <code>padframe.raw.gds</code> / <code>padframe.gds</code>
* '''Magic Layout:''' <code>padframe.mag</code>
* '''SPICE Extracted Netlist:''' <code>padframe.spice</code>
* '''Simulation Models:''' <code>model.spice</code> / <code>design_header.ngspice</code>

[[index.php?title=Category:LibreSilicon Verification Reports]]
[[index.php?title=Category:LibrePDK]]
[[index.php?title=Category:SG13G2]]

LibrePDK Padframe SPICE Verification Report GF180A@3.3V

2026-09-01T16:39:56Z

Leviathan:

= LibrePDK Padframe SPICE Verification Report =

'''Technology:''' IHP SG13G2 (130nm BiCMOS)
'''Operating Voltage:''' 3.3 V
'''Verification Date:''' 2026-09-01 16:01:45 UTC
'''Extracted Netlist:''' <code>padframe.spice</code> (Magic VLSI Hierarchical Extraction)

== Executive Summary ==
{| class="wikitable" style="text-align:center; width:90%;"
! Test Scenario !! Target Net / Pad !! Measured Values !! Design Specification !! Status
|-
| style="text-align:left;" | '''ESD Clamping Transient''' || PAD_GPIO_0 (ESD Clamps) || Peak Clamped: 4.30 V || < 15.0 V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Output Drive (Write)''' || gpio_out_0 → PAD_GPIO_0 || Low: 2.84 V, High: 0.65 V || Rail-to-rail driver transition || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Input Sensing (Read / Hi-Z)''' || PAD_GPIO_1 → gpio_in_1 || Pad 0V → 0.00 V, Pad 3.3V → 2.87 V || Pad 0V -> Core > 0.8V, Pad 3.3V -> Core < 0.2V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Pad-to-Pad Dynamic Loopback''' || PAD_GPIO_0 → PAD_GPIO_1 || Bus: 1.40V / 1.37V | Rx: 2.85V / -0.01V || Full rail-to-rail dynamic loopback across frame || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|}

== Core Signal & Bonding Pad Interface Mapping ==
The LibrePDK padframe generator exposed unique net names defined in the JSON configuration for seamless Coriolis LEF/DEF digital core integration:

{| class="wikitable" style="width:90%; font-family:monospace;"
! Subcircuit Port Name !! Direction !! Interface Type !! Associated Physical Layer
|-
| '''VDD''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''VSS''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''gpio_in_0''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_0''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_0''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_0''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''gpio_in_1''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_1''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_1''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_1''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_miso_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_miso_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_miso_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MISO''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_cs_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_cs_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_cs_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_CS''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_tx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_tx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_tx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_TX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_rx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_rx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_rx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_RX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_sclk_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_sclk_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_sclk_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_SCLK''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_mosi_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_mosi_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_mosi_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MOSI''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|}

== Transient Simulation Waveforms ==

=== 1. ESD Clamping Event ===
Transient simulation applying a 2kV / 1.33A peak Human Body Model (HBM) current pulse directly to the bonding pad:
[[File:Sim 1 esd clamping GF180A@3.3V.png|thumb|center|700px|ESD Diode and Rail Clamping Response under 1.33A Transient Current Pulse]]

=== 2. Digital Output Drive (Write) ===
Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:
[[File:Sim 2 signal write GF180A@3.3V.png|thumb|center|700px|Signal Write: Core OUT driving Bonding Pad (0V to 3.3V)]]

=== 3. Digital Input Sensing (Read / Hi-Z) ===
External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:
[[File:Sim 3 signal read hiz GF180A@3.3V.png|thumb|center|700px|Signal Read: External Bonding Pad voltage sensed at Core IN]]

=== 4. Full Dynamic Loopback ===
End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):
[[File:File:Sim 4 pad to pad loopback GF180A@3.3V.png|thumb|center|700px|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]

== Physical Verification & GDS Delivery ==
* '''GDSII Top Level:''' <code>padframe.raw.gds</code> / <code>padframe.gds</code>
* '''Magic Layout:''' <code>padframe.mag</code>
* '''SPICE Extracted Netlist:''' <code>padframe.spice</code>
* '''Simulation Models:''' <code>model.spice</code> / <code>design_header.ngspice</code>

[[index.php?title=Category:LibreSilicon Verification Reports]]
[[index.php?title=Category:LibrePDK]]
[[index.php?title=Category:SG13G2]]

LibrePDK Padframe SPICE Verification Report GF180A@3.3V

2026-09-01T16:39:29Z

Leviathan: /* 4. Full Dynamic Loopback */

= LibrePDK Padframe SPICE Verification Report =

'''Technology:''' IHP SG13G2 (130nm BiCMOS)
'''Operating Voltage:''' 3.3 V
'''Verification Date:''' 2026-09-01 16:01:45 UTC
'''Extracted Netlist:''' <code>padframe.spice</code> (Magic VLSI Hierarchical Extraction)

== Executive Summary ==
{| class="wikitable" style="text-align:center; width:90%;"
! Test Scenario !! Target Net / Pad !! Measured Values !! Design Specification !! Status
|-
| style="text-align:left;" | '''ESD Clamping Transient''' || PAD_GPIO_0 (ESD Clamps) || Peak Clamped: 4.30 V || < 15.0 V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Output Drive (Write)''' || gpio_out_0 → PAD_GPIO_0 || Low: 2.84 V, High: 0.65 V || Rail-to-rail driver transition || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Input Sensing (Read / Hi-Z)''' || PAD_GPIO_1 → gpio_in_1 || Pad 0V → 0.00 V, Pad 3.3V → 2.87 V || Pad 0V -> Core > 0.8V, Pad 3.3V -> Core < 0.2V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Pad-to-Pad Dynamic Loopback''' || PAD_GPIO_0 → PAD_GPIO_1 || Bus: 1.40V / 1.37V | Rx: 2.85V / -0.01V || Full rail-to-rail dynamic loopback across frame || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|}

== Core Signal & Bonding Pad Interface Mapping ==
The LibrePDK padframe generator exposed unique net names defined in the JSON configuration for seamless Coriolis LEF/DEF digital core integration:

{| class="wikitable" style="width:90%; font-family:monospace;"
! Subcircuit Port Name !! Direction !! Interface Type !! Associated Physical Layer
|-
| '''VDD''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''VSS''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''gpio_in_0''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_0''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_0''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_0''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''gpio_in_1''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_1''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_1''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_1''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_miso_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_miso_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_miso_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MISO''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_cs_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_cs_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_cs_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_CS''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_tx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_tx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_tx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_TX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_rx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_rx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_rx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_RX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_sclk_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_sclk_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_sclk_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_SCLK''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_mosi_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_mosi_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_mosi_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MOSI''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|}

== Transient Simulation Waveforms ==

=== 1. ESD Clamping Event ===
Transient simulation applying a 2kV / 1.33A peak Human Body Model (HBM) current pulse directly to the bonding pad:
[[File:Sim 1 esd clamping GF180A@3.3V.png|thumb|center|700px|ESD Diode and Rail Clamping Response under 1.33A Transient Current Pulse]]

=== 2. Digital Output Drive (Write) ===
Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:
[[File:Sim 2 signal write GF180A@3.3V.png|thumb|center|700px|Signal Write: Core OUT driving Bonding Pad (0V to 3.3V)]]

=== 3. Digital Input Sensing (Read / Hi-Z) ===
External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:
☢
[[File:Sim 3 signal read hiz GF180A@3.3V.png|thumb|center|700px|Signal Read: External Bonding Pad voltage sensed at Core IN]]

=== 4. Full Dynamic Loopback ===
End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):
☢
[[File:File:Sim 4 pad to pad loopback GF180A@3.3V.png|thumb|center|700px|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]

== Physical Verification & GDS Delivery ==
* '''GDSII Top Level:''' <code>padframe.raw.gds</code> / <code>padframe.gds</code>
* '''Magic Layout:''' <code>padframe.mag</code>
* '''SPICE Extracted Netlist:''' <code>padframe.spice</code>
* '''Simulation Models:''' <code>model.spice</code> / <code>design_header.ngspice</code>

[[index.php?title=Category:LibreSilicon Verification Reports]]
[[index.php?title=Category:LibrePDK]]
[[index.php?title=Category:SG13G2]]

LibrePDK Padframe SPICE Verification Report GF180A@3.3V

2026-09-01T16:39:11Z

Leviathan: /* 3. Digital Input Sensing (Read / Hi-Z) */

= LibrePDK Padframe SPICE Verification Report =

'''Technology:''' IHP SG13G2 (130nm BiCMOS)
'''Operating Voltage:''' 3.3 V
'''Verification Date:''' 2026-09-01 16:01:45 UTC
'''Extracted Netlist:''' <code>padframe.spice</code> (Magic VLSI Hierarchical Extraction)

== Executive Summary ==
{| class="wikitable" style="text-align:center; width:90%;"
! Test Scenario !! Target Net / Pad !! Measured Values !! Design Specification !! Status
|-
| style="text-align:left;" | '''ESD Clamping Transient''' || PAD_GPIO_0 (ESD Clamps) || Peak Clamped: 4.30 V || < 15.0 V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Output Drive (Write)''' || gpio_out_0 → PAD_GPIO_0 || Low: 2.84 V, High: 0.65 V || Rail-to-rail driver transition || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Input Sensing (Read / Hi-Z)''' || PAD_GPIO_1 → gpio_in_1 || Pad 0V → 0.00 V, Pad 3.3V → 2.87 V || Pad 0V -> Core > 0.8V, Pad 3.3V -> Core < 0.2V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Pad-to-Pad Dynamic Loopback''' || PAD_GPIO_0 → PAD_GPIO_1 || Bus: 1.40V / 1.37V | Rx: 2.85V / -0.01V || Full rail-to-rail dynamic loopback across frame || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|}

== Core Signal & Bonding Pad Interface Mapping ==
The LibrePDK padframe generator exposed unique net names defined in the JSON configuration for seamless Coriolis LEF/DEF digital core integration:

{| class="wikitable" style="width:90%; font-family:monospace;"
! Subcircuit Port Name !! Direction !! Interface Type !! Associated Physical Layer
|-
| '''VDD''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''VSS''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''gpio_in_0''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_0''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_0''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_0''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''gpio_in_1''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_1''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_1''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_1''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_miso_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_miso_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_miso_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MISO''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_cs_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_cs_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_cs_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_CS''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_tx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_tx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_tx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_TX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_rx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_rx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_rx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_RX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_sclk_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_sclk_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_sclk_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_SCLK''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_mosi_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_mosi_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_mosi_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MOSI''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|}

== Transient Simulation Waveforms ==

=== 1. ESD Clamping Event ===
Transient simulation applying a 2kV / 1.33A peak Human Body Model (HBM) current pulse directly to the bonding pad:
[[File:Sim 1 esd clamping GF180A@3.3V.png|thumb|center|700px|ESD Diode and Rail Clamping Response under 1.33A Transient Current Pulse]]

=== 2. Digital Output Drive (Write) ===
Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:
[[File:Sim 2 signal write GF180A@3.3V.png|thumb|center|700px|Signal Write: Core OUT driving Bonding Pad (0V to 3.3V)]]

=== 3. Digital Input Sensing (Read / Hi-Z) ===
External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:
☢
[[File:Sim 3 signal read hiz GF180A@3.3V.png|thumb|center|700px|Signal Read: External Bonding Pad voltage sensed at Core IN]]

=== 4. Full Dynamic Loopback ===
End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):

[[File:Sim 4 pad to pad loopback GF180A@3.3V.png|none|thumb]]
☢

[[File:sim_4_pad_to_pad_loopback.png|thumb|center|700px|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]

== Physical Verification & GDS Delivery ==
* '''GDSII Top Level:''' <code>padframe.raw.gds</code> / <code>padframe.gds</code>
* '''Magic Layout:''' <code>padframe.mag</code>
* '''SPICE Extracted Netlist:''' <code>padframe.spice</code>
* '''Simulation Models:''' <code>model.spice</code> / <code>design_header.ngspice</code>

[[index.php?title=Category:LibreSilicon Verification Reports]]
[[index.php?title=Category:LibrePDK]]
[[index.php?title=Category:SG13G2]]

LibrePDK Padframe SPICE Verification Report GF180A@3.3V

2026-09-01T16:38:55Z

Leviathan: /* 2. Digital Output Drive (Write) */

= LibrePDK Padframe SPICE Verification Report =

'''Technology:''' IHP SG13G2 (130nm BiCMOS)
'''Operating Voltage:''' 3.3 V
'''Verification Date:''' 2026-09-01 16:01:45 UTC
'''Extracted Netlist:''' <code>padframe.spice</code> (Magic VLSI Hierarchical Extraction)

== Executive Summary ==
{| class="wikitable" style="text-align:center; width:90%;"
! Test Scenario !! Target Net / Pad !! Measured Values !! Design Specification !! Status
|-
| style="text-align:left;" | '''ESD Clamping Transient''' || PAD_GPIO_0 (ESD Clamps) || Peak Clamped: 4.30 V || < 15.0 V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Output Drive (Write)''' || gpio_out_0 → PAD_GPIO_0 || Low: 2.84 V, High: 0.65 V || Rail-to-rail driver transition || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Input Sensing (Read / Hi-Z)''' || PAD_GPIO_1 → gpio_in_1 || Pad 0V → 0.00 V, Pad 3.3V → 2.87 V || Pad 0V -> Core > 0.8V, Pad 3.3V -> Core < 0.2V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Pad-to-Pad Dynamic Loopback''' || PAD_GPIO_0 → PAD_GPIO_1 || Bus: 1.40V / 1.37V | Rx: 2.85V / -0.01V || Full rail-to-rail dynamic loopback across frame || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|}

== Core Signal & Bonding Pad Interface Mapping ==
The LibrePDK padframe generator exposed unique net names defined in the JSON configuration for seamless Coriolis LEF/DEF digital core integration:

{| class="wikitable" style="width:90%; font-family:monospace;"
! Subcircuit Port Name !! Direction !! Interface Type !! Associated Physical Layer
|-
| '''VDD''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''VSS''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''gpio_in_0''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_0''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_0''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_0''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''gpio_in_1''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_1''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_1''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_1''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_miso_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_miso_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_miso_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MISO''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_cs_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_cs_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_cs_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_CS''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_tx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_tx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_tx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_TX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_rx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_rx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_rx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_RX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_sclk_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_sclk_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_sclk_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_SCLK''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_mosi_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_mosi_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_mosi_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MOSI''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|}

== Transient Simulation Waveforms ==

=== 1. ESD Clamping Event ===
Transient simulation applying a 2kV / 1.33A peak Human Body Model (HBM) current pulse directly to the bonding pad:
[[File:Sim 1 esd clamping GF180A@3.3V.png|thumb|center|700px|ESD Diode and Rail Clamping Response under 1.33A Transient Current Pulse]]

=== 2. Digital Output Drive (Write) ===
Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:
[[File:Sim 2 signal write GF180A@3.3V.png|thumb|center|700px|Signal Write: Core OUT driving Bonding Pad (0V to 3.3V)]]

=== 3. Digital Input Sensing (Read / Hi-Z) ===
External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:
[[File:Sim 3 signal read hiz GF180A@3.3V.png|none|thumb]]
☢

[[File:sim_3_signal_read_hiz.png|thumb|center|700px|Signal Read: External Bonding Pad voltage sensed at Core IN]]

=== 4. Full Dynamic Loopback ===
End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):

[[File:Sim 4 pad to pad loopback GF180A@3.3V.png|none|thumb]]
☢

[[File:sim_4_pad_to_pad_loopback.png|thumb|center|700px|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]

== Physical Verification & GDS Delivery ==
* '''GDSII Top Level:''' <code>padframe.raw.gds</code> / <code>padframe.gds</code>
* '''Magic Layout:''' <code>padframe.mag</code>
* '''SPICE Extracted Netlist:''' <code>padframe.spice</code>
* '''Simulation Models:''' <code>model.spice</code> / <code>design_header.ngspice</code>

[[index.php?title=Category:LibreSilicon Verification Reports]]
[[index.php?title=Category:LibrePDK]]
[[index.php?title=Category:SG13G2]]

LibrePDK Padframe SPICE Verification Report GF180A@3.3V

2026-09-01T16:38:39Z

Leviathan: /* 2. Digital Output Drive (Write) */

= LibrePDK Padframe SPICE Verification Report =

'''Technology:''' IHP SG13G2 (130nm BiCMOS)
'''Operating Voltage:''' 3.3 V
'''Verification Date:''' 2026-09-01 16:01:45 UTC
'''Extracted Netlist:''' <code>padframe.spice</code> (Magic VLSI Hierarchical Extraction)

== Executive Summary ==
{| class="wikitable" style="text-align:center; width:90%;"
! Test Scenario !! Target Net / Pad !! Measured Values !! Design Specification !! Status
|-
| style="text-align:left;" | '''ESD Clamping Transient''' || PAD_GPIO_0 (ESD Clamps) || Peak Clamped: 4.30 V || < 15.0 V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Output Drive (Write)''' || gpio_out_0 → PAD_GPIO_0 || Low: 2.84 V, High: 0.65 V || Rail-to-rail driver transition || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Input Sensing (Read / Hi-Z)''' || PAD_GPIO_1 → gpio_in_1 || Pad 0V → 0.00 V, Pad 3.3V → 2.87 V || Pad 0V -> Core > 0.8V, Pad 3.3V -> Core < 0.2V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Pad-to-Pad Dynamic Loopback''' || PAD_GPIO_0 → PAD_GPIO_1 || Bus: 1.40V / 1.37V | Rx: 2.85V / -0.01V || Full rail-to-rail dynamic loopback across frame || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|}

== Core Signal & Bonding Pad Interface Mapping ==
The LibrePDK padframe generator exposed unique net names defined in the JSON configuration for seamless Coriolis LEF/DEF digital core integration:

{| class="wikitable" style="width:90%; font-family:monospace;"
! Subcircuit Port Name !! Direction !! Interface Type !! Associated Physical Layer
|-
| '''VDD''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''VSS''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''gpio_in_0''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_0''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_0''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_0''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''gpio_in_1''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_1''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_1''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_1''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_miso_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_miso_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_miso_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MISO''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_cs_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_cs_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_cs_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_CS''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_tx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_tx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_tx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_TX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_rx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_rx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_rx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_RX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_sclk_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_sclk_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_sclk_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_SCLK''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_mosi_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_mosi_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_mosi_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MOSI''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|}

== Transient Simulation Waveforms ==

=== 1. ESD Clamping Event ===
Transient simulation applying a 2kV / 1.33A peak Human Body Model (HBM) current pulse directly to the bonding pad:
[[File:Sim 1 esd clamping GF180A@3.3V.png|thumb|center|700px|ESD Diode and Rail Clamping Response under 1.33A Transient Current Pulse]]

=== 2. Digital Output Drive (Write) ===
Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:
[[File:Sim 2 signal write GF180A@3.3V.png|none|thumb]]

[[File:sim_2_signal_write.png|thumb|center|700px|Signal Write: Core OUT driving Bonding Pad (0V to 3.3V)]]

=== 3. Digital Input Sensing (Read / Hi-Z) ===
External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:
[[File:Sim 3 signal read hiz GF180A@3.3V.png|none|thumb]]
☢

[[File:sim_3_signal_read_hiz.png|thumb|center|700px|Signal Read: External Bonding Pad voltage sensed at Core IN]]

=== 4. Full Dynamic Loopback ===
End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):

[[File:Sim 4 pad to pad loopback GF180A@3.3V.png|none|thumb]]
☢

[[File:sim_4_pad_to_pad_loopback.png|thumb|center|700px|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]

== Physical Verification & GDS Delivery ==
* '''GDSII Top Level:''' <code>padframe.raw.gds</code> / <code>padframe.gds</code>
* '''Magic Layout:''' <code>padframe.mag</code>
* '''SPICE Extracted Netlist:''' <code>padframe.spice</code>
* '''Simulation Models:''' <code>model.spice</code> / <code>design_header.ngspice</code>

[[index.php?title=Category:LibreSilicon Verification Reports]]
[[index.php?title=Category:LibrePDK]]
[[index.php?title=Category:SG13G2]]

File:Sim 4 pad to pad loopback GF180A@3.3V.png

2026-09-01T16:38:30Z

Leviathan:

Sim 4 pad to pad loopback GF180A@3.3V

File:Sim 3 signal read hiz GF180A@3.3V.png

2026-09-01T16:38:06Z

Leviathan:

Sim 3 signal read hiz GF180A@3.3V

File:Sim 2 signal write GF180A@3.3V.png

2026-09-01T16:37:41Z

Leviathan:

Sim 2 signal write GF180A@3.3V

LibrePDK Padframe SPICE Verification Report GF180A@3.3V

2026-09-01T16:37:12Z

Leviathan:

= LibrePDK Padframe SPICE Verification Report =

'''Technology:''' IHP SG13G2 (130nm BiCMOS)
'''Operating Voltage:''' 3.3 V
'''Verification Date:''' 2026-09-01 16:01:45 UTC
'''Extracted Netlist:''' <code>padframe.spice</code> (Magic VLSI Hierarchical Extraction)

== Executive Summary ==
{| class="wikitable" style="text-align:center; width:90%;"
! Test Scenario !! Target Net / Pad !! Measured Values !! Design Specification !! Status
|-
| style="text-align:left;" | '''ESD Clamping Transient''' || PAD_GPIO_0 (ESD Clamps) || Peak Clamped: 4.30 V || < 15.0 V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Output Drive (Write)''' || gpio_out_0 → PAD_GPIO_0 || Low: 2.84 V, High: 0.65 V || Rail-to-rail driver transition || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Input Sensing (Read / Hi-Z)''' || PAD_GPIO_1 → gpio_in_1 || Pad 0V → 0.00 V, Pad 3.3V → 2.87 V || Pad 0V -> Core > 0.8V, Pad 3.3V -> Core < 0.2V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Pad-to-Pad Dynamic Loopback''' || PAD_GPIO_0 → PAD_GPIO_1 || Bus: 1.40V / 1.37V | Rx: 2.85V / -0.01V || Full rail-to-rail dynamic loopback across frame || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|}

== Core Signal & Bonding Pad Interface Mapping ==
The LibrePDK padframe generator exposed unique net names defined in the JSON configuration for seamless Coriolis LEF/DEF digital core integration:

{| class="wikitable" style="width:90%; font-family:monospace;"
! Subcircuit Port Name !! Direction !! Interface Type !! Associated Physical Layer
|-
| '''VDD''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''VSS''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''gpio_in_0''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_0''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_0''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_0''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''gpio_in_1''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_1''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_1''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_1''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_miso_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_miso_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_miso_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MISO''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_cs_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_cs_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_cs_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_CS''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_tx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_tx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_tx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_TX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_rx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_rx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_rx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_RX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_sclk_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_sclk_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_sclk_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_SCLK''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_mosi_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_mosi_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_mosi_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MOSI''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|}

== Transient Simulation Waveforms ==

=== 1. ESD Clamping Event ===
Transient simulation applying a 2kV / 1.33A peak Human Body Model (HBM) current pulse directly to the bonding pad:
[[File:Sim 1 esd clamping GF180A@3.3V.png|thumb|center|700px|ESD Diode and Rail Clamping Response under 1.33A Transient Current Pulse]]

=== 2. Digital Output Drive (Write) ===
Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:

[[File:sim_2_signal_write.png|thumb|center|700px|Signal Write: Core OUT driving Bonding Pad (0V to 3.3V)]]

=== 3. Digital Input Sensing (Read / Hi-Z) ===
External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:

[[File:sim_3_signal_read_hiz.png|thumb|center|700px|Signal Read: External Bonding Pad voltage sensed at Core IN]]

=== 4. Full Dynamic Loopback ===
End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):

[[File:sim_4_pad_to_pad_loopback.png|thumb|center|700px|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]

== Physical Verification & GDS Delivery ==
* '''GDSII Top Level:''' <code>padframe.raw.gds</code> / <code>padframe.gds</code>
* '''Magic Layout:''' <code>padframe.mag</code>
* '''SPICE Extracted Netlist:''' <code>padframe.spice</code>
* '''Simulation Models:''' <code>model.spice</code> / <code>design_header.ngspice</code>

[[index.php?title=Category:LibreSilicon Verification Reports]]
[[index.php?title=Category:LibrePDK]]
[[index.php?title=Category:SG13G2]]

LibrePDK Padframe SPICE Verification Report GF180A@3.3V

2026-09-01T16:36:44Z

Leviathan:

[[File:Sim 1 esd clamping GF180A@3.3V.png|none|thumb]]

= LibrePDK Padframe SPICE Verification Report =

'''Technology:''' IHP SG13G2 (130nm BiCMOS)
'''Operating Voltage:''' 3.3 V
'''Verification Date:''' 2026-09-01 16:01:45 UTC
'''Extracted Netlist:''' <code>padframe.spice</code> (Magic VLSI Hierarchical Extraction)

== Executive Summary ==
{| class="wikitable" style="text-align:center; width:90%;"
! Test Scenario !! Target Net / Pad !! Measured Values !! Design Specification !! Status
|-
| style="text-align:left;" | '''ESD Clamping Transient''' || PAD_GPIO_0 (ESD Clamps) || Peak Clamped: 4.30 V || < 15.0 V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Output Drive (Write)''' || gpio_out_0 → PAD_GPIO_0 || Low: 2.84 V, High: 0.65 V || Rail-to-rail driver transition || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Input Sensing (Read / Hi-Z)''' || PAD_GPIO_1 → gpio_in_1 || Pad 0V → 0.00 V, Pad 3.3V → 2.87 V || Pad 0V -> Core > 0.8V, Pad 3.3V -> Core < 0.2V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Pad-to-Pad Dynamic Loopback''' || PAD_GPIO_0 → PAD_GPIO_1 || Bus: 1.40V / 1.37V | Rx: 2.85V / -0.01V || Full rail-to-rail dynamic loopback across frame || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|}

== Core Signal & Bonding Pad Interface Mapping ==
The LibrePDK padframe generator exposed unique net names defined in the JSON configuration for seamless Coriolis LEF/DEF digital core integration:

{| class="wikitable" style="width:90%; font-family:monospace;"
! Subcircuit Port Name !! Direction !! Interface Type !! Associated Physical Layer
|-
| '''VDD''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''VSS''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''gpio_in_0''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_0''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_0''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_0''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''gpio_in_1''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_1''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_1''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_1''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_miso_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_miso_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_miso_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MISO''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_cs_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_cs_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_cs_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_CS''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_tx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_tx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_tx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_TX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_rx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_rx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_rx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_RX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_sclk_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_sclk_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_sclk_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_SCLK''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_mosi_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_mosi_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_mosi_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MOSI''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|}

== Transient Simulation Waveforms ==

=== 1. ESD Clamping Event ===
Transient simulation applying a 2kV / 1.33A peak Human Body Model (HBM) current pulse directly to the bonding pad:
[[File:sim_1_esd_clamping.png|thumb|center|700px|ESD Diode and Rail Clamping Response under 1.33A Transient Current Pulse]]

=== 2. Digital Output Drive (Write) ===
Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:
[[File:sim_2_signal_write.png|thumb|center|700px|Signal Write: Core OUT driving Bonding Pad (0V to 3.3V)]]

=== 3. Digital Input Sensing (Read / Hi-Z) ===
External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:
[[File:sim_3_signal_read_hiz.png|thumb|center|700px|Signal Read: External Bonding Pad voltage sensed at Core IN]]

=== 4. Full Dynamic Loopback ===
End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):
[[File:sim_4_pad_to_pad_loopback.png|thumb|center|700px|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]

== Physical Verification & GDS Delivery ==
* '''GDSII Top Level:''' <code>padframe.raw.gds</code> / <code>padframe.gds</code>
* '''Magic Layout:''' <code>padframe.mag</code>
* '''SPICE Extracted Netlist:''' <code>padframe.spice</code>
* '''Simulation Models:''' <code>model.spice</code> / <code>design_header.ngspice</code>

[[index.php?title=Category:LibreSilicon Verification Reports]]
[[index.php?title=Category:LibrePDK]]
[[index.php?title=Category:SG13G2]]

File:Sim 1 esd clamping GF180A@3.3V.png

2026-09-01T16:36:27Z

Leviathan:

Sim 1 esd clamping GF180A@3.3V

Pad Frame Generator

2026-09-01T16:35:51Z

Leviathan: /* Test cases */

[[File:Padframe Example.png|thumb|Example of a pad frame for SG13G2@1.2V]]
The Pad Frame Generator is part of the [[LibrePDK]] and provides the [[Pad Cell Generator]] functionality.

It's job is to assemble a ready to use pad frame harness, with ESD protection and power rail wire width properly adjusted for accommodating the intended current driving capacity as well as the intended voltage levels to be used.

== Types of Pad Cells produced ==
Currently we support only simple IO [[Pad Cell]], analog cells, and power cells, complex pad cells still are being in development.

The very special impedance compensated pad cell in the works ([[High-Speed Impedance-Compensated Pad Cell]]) is needed in order to hook up DDR4 RAM to our chips or build a PCIe device.

== How to use ==
There are two options on how you can run the Pad Frame Generator on your machine, you can go the easy route and use a docker container or you can [[Pad Frame Generator#Installation|set up LibrePDK locally]].

An example for a paframe config can be found here [https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/tests/padframes/padframe_sg13g2_1v2.json?ref_type=heads padframe_sg13g2_1v2.json]

=== Docker ===
First pull the docker image for the [[LibrePDK]] in order to make sure the image is up to date by running<syntaxhighlight lang="bash">
docker pull leviathanch/librepdk:latest
</syntaxhighlight>Then you can feed your JSON config for the padframe you have configured to the pad frame generator script contained in the docker image.

<syntaxhighlight lang="bash">docker run -it --rm \
-e HOST_UID=$(id -u) -e HOST_GID=$(id -g) \
-v "$(pwd)":/workspace leviathanch/librepdk:latest \
librepdk_padframe_generator -i padframe_config.json \
-o my_padframe</syntaxhighlight>After running the generator you should have a folder named my_padframe containing the LEF, DEF, Magic and all the other files you need for running a full synthesis flow of your designs.

=== Run Locally ===
After [[Pad Frame Generator#Installation|seting up LibrePDK locally]] you can generate your pad frame by running<syntaxhighlight lang="bash">uv run \
librepdk_padframe_generator -i padframe_config.json \
-o my_padframe</syntaxhighlight>

== Test cases ==
Proper ESD and switching behavior has been verified for all supported technologies in LibrePDK and reports for two of the most important test cases have been put onto our wiki page.

SG13G2 is important because it's a complex high frequency process with many metal layers plus there is an opportunity for cooperating in a tapeout.

GF180A only has 3 metal layers which best represents low tech nodes, so it was important to verify that we also can produce working pad frames for such a low metal count process.

Tests have been performed for the sample pad frame configurations for [https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/tests/padframes/padframe_gf180a_3v3.json?ref_type=heads IHP's SG13G2 at 1.2V] and the [https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/tests/padframes/padframe_gf180a_3v3.json?ref_type=heads GF180A process at 3.3V] (by Global Foundries).

Please look at [[LibrePDK Padframe SPICE Verification Report SG13G2@1.2V]] and [[LibrePDK Padframe SPICE Verification Report GF180A@3.3V]] for the simulation verification results and wave forms.

== Installation ==
Since the Pad Frame Generator is part of [[LibrePDK]] you can find the guide on how to install all the dependencies in the [[LibrePDK#Installation|Installation section of the LibrePDK]] page

== Benchmarks ==
Generating all those individual geometries takes a lot of time, an initial generation run can take up to half an hour due to the complexity and size of a pad frame and its pad cells, which is why we introduced component caching.

=== Initial run ===
The initial run for GF180A takes around 20 minutes, IHP and Skywater with even more layers can take up to 32 minutes<syntaxhighlight lang="bash">
real 20m48.886s
user 20m46.885s
sys 0m3.880s
</syntaxhighlight>

=== Further runs ===
During the second run that generation time is cut in half when assembling the padframe and writing it out.<syntaxhighlight lang="bash">
real 8m43.972s
user 8m40.889s
sys 0m4.139s
</syntaxhighlight>

LibrePDK Padframe SPICE Verification Report SG13G2@1.2V

2026-09-01T16:17:03Z

Leviathan: /* Physical Verification & GDS Delivery */

= LibrePDK Padframe SPICE Verification Report =

'''Technology:''' IHP SG13G2 (130nm BiCMOS)
'''Operating Voltage:''' 1.2 V
'''Verification Date:''' 2026-09-01 16:47:40 UTC
'''Extracted Netlist:''' <code>padframe.spice</code> (Magic VLSI Hierarchical Extraction)

== Executive Summary ==
{| class="wikitable" style="text-align:center; width:90%;"
! Test Scenario !! Target Net / Pad !! Measured Values !! Design Specification !! Status
|-
| style="text-align:left;" | '''ESD Clamping Transient''' || PAD_GPIO_0 (ESD Clamps) || Peak Clamped: 2.75 V || < 15.0 V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Output Drive (Write)''' || gpio_out_0 → PAD_GPIO_0 || Low: 0.00 V, High: 1.15 V || Rail-to-rail driver transition || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Input Sensing (Read / Hi-Z)''' || PAD_GPIO_1 → gpio_in_1 || Pad 0V → 0.00 V, Pad 1.2V → 1.15 V || Pad 0V -> Core > 0.8V, Pad 1.2V -> Core < 0.2V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Pad-to-Pad Dynamic Loopback''' || PAD_GPIO_0 → PAD_GPIO_1 || Bus: 0.12V / 1.20V | Rx: 0.00V / 1.15V || Full rail-to-rail dynamic loopback across frame || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|}

== Core Signal & Bonding Pad Interface Mapping ==
The LibrePDK padframe generator exposed unique net names defined in the JSON configuration for seamless Coriolis LEF/DEF digital core integration:

{| class="wikitable" style="width:90%; font-family:monospace;"
! Subcircuit Port Name !! Direction !! Interface Type !! Associated Physical Layer
|-
| '''VDD''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''VSS''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''gpio_in_0''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_0''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_0''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_0''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''gpio_in_1''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_1''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_1''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_1''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_miso_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_miso_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_miso_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MISO''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_cs_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_cs_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_cs_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_CS''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_tx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_tx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_tx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_TX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_rx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_rx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_rx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_RX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_sclk_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_sclk_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_sclk_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_SCLK''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_mosi_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_mosi_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_mosi_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MOSI''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|}

== Transient Simulation Waveforms ==

=== 1. ESD Clamping Event ===
Transient simulation applying a 2kV / 1.33A peak Human Body Model (HBM) current pulse directly to the bonding pad:
☢
[[File:Sim 1 esd clamping SG13G2@1.2V.png|thumb|center|700px|ESD Diode and Rail Clamping Response under 1.33A Transient Current Pulse]]

=== 2. Digital Output Drive (Write) ===
Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:
☢
[[File:Sim 2 signal write SG13G2@1.2V.png|thumb|center|700px|Signal Write: Core OUT driving Bonding Pad (0V to 1.2V)]]

=== 3. Digital Input Sensing (Read / Hi-Z) ===
External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:
[[File:Sim 3 signal read hiz SG13G2@1.2V.png|thumb|center|700px|Signal Read: External Bonding Pad voltage sensed at Core IN]]

=== 4. Full Dynamic Loopback ===
End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):
[[File:Sim 4 pad to pad loopback SG13G2@1.2V.png|thumb|center|700px|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]

== Physical Verification & GDS Delivery ==
* '''GDSII Top Level:''' <code>padframe.raw.gds</code> / <code>padframe.gds</code>
* '''Magic Layout:''' <code>padframe.mag</code>
* '''SPICE Extracted Netlist:''' <code>padframe.spice</code>
* '''Simulation Models:''' <code>model.spice</code> / <code>design_header.ngspice</code>

LibrePDK Padframe SPICE Verification Report SG13G2@1.2V

2026-09-01T16:16:46Z

Leviathan:

LibrePDK Padframe SPICE Verification Report SG13G2@1.2V

2026-09-01T16:15:06Z

Leviathan: /* 3. Digital Input Sensing (Read / Hi-Z) */

= LibrePDK Padframe SPICE Verification Report =

'''Technology:''' IHP SG13G2 (130nm BiCMOS)
'''Operating Voltage:''' 1.2 V
'''Verification Date:''' 2026-09-01 16:47:40 UTC
'''Extracted Netlist:''' <code>padframe.spice</code> (Magic VLSI Hierarchical Extraction)

== Executive Summary ==
{| class="wikitable" style="text-align:center; width:90%;"
! Test Scenario !! Target Net / Pad !! Measured Values !! Design Specification !! Status
|-
| style="text-align:left;" | '''ESD Clamping Transient''' || PAD_GPIO_0 (ESD Clamps) || Peak Clamped: 2.75 V || < 15.0 V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Output Drive (Write)''' || gpio_out_0 → PAD_GPIO_0 || Low: 0.00 V, High: 1.15 V || Rail-to-rail driver transition || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Input Sensing (Read / Hi-Z)''' || PAD_GPIO_1 → gpio_in_1 || Pad 0V → 0.00 V, Pad 1.2V → 1.15 V || Pad 0V -> Core > 0.8V, Pad 1.2V -> Core < 0.2V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Pad-to-Pad Dynamic Loopback''' || PAD_GPIO_0 → PAD_GPIO_1 || Bus: 0.12V / 1.20V | Rx: 0.00V / 1.15V || Full rail-to-rail dynamic loopback across frame || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|}

== Core Signal & Bonding Pad Interface Mapping ==
The LibrePDK padframe generator exposed unique net names defined in the JSON configuration for seamless Coriolis LEF/DEF digital core integration:

{| class="wikitable" style="width:90%; font-family:monospace;"
! Subcircuit Port Name !! Direction !! Interface Type !! Associated Physical Layer
|-
| '''VDD''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''VSS''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''gpio_in_0''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_0''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_0''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_0''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''gpio_in_1''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_1''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_1''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_1''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_miso_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_miso_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_miso_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MISO''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_cs_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_cs_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_cs_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_CS''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_tx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_tx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_tx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_TX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_rx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_rx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_rx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_RX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_sclk_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_sclk_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_sclk_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_SCLK''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_mosi_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_mosi_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_mosi_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MOSI''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|}

== Transient Simulation Waveforms ==

=== 1. ESD Clamping Event ===
Transient simulation applying a 2kV / 1.33A peak Human Body Model (HBM) current pulse directly to the bonding pad:
[[File:Sim 1 esd clamping SG13G2@1.2V.png|none|thumb]]
☢
[[File:sim_1_esd_clamping.png|thumb|center|700px|ESD Diode and Rail Clamping Response under 1.33A Transient Current Pulse]]

=== 2. Digital Output Drive (Write) ===
Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:
[[File:Sim 2 signal write SG13G2@1.2V.png|none|thumb]]
☢
[[File:sim_2_signal_write.png|thumb|center|700px|Signal Write: Core OUT driving Bonding Pad (0V to 1.2V)]]

=== 3. Digital Input Sensing (Read / Hi-Z) ===
External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:
[[File:Sim 3 signal read hiz SG13G2@1.2V.png|none|thumb]]
File:Sim 2 signal write.pngSignal Write: Core OUT driving Bonding Pad (0V to 1.2V)
[[File:sim_3_signal_read_hiz.png|thumb|center|700px|Signal Read: External Bonding Pad voltage sensed at Core IN]]

=== 4. Full Dynamic Loopback ===
End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):
[[File:Sim 4 pad to pad loopback SG13G2@1.2V.png|thumb|center|700px|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]

== Physical Verification & GDS Delivery ==
* '''GDSII Top Level:''' <code>padframe.raw.gds</code> / <code>padframe.gds</code>
* '''Magic Layout:''' <code>padframe.mag</code>
* '''SPICE Extracted Netlist:''' <code>padframe.spice</code>
* '''Simulation Models:''' <code>model.spice</code> / <code>design_header.ngspice</code>

[[index.php?title=Category:LibreSilicon Verification Reports]]
[[index.php?title=Category:LibrePDK]]
[[index.php?title=Category:SG13G2]]

File:Sim 1 esd clamping SG13G2@1.2V.png

2026-09-01T16:14:53Z

Leviathan:

Sim 1 esd clamping SG13G2@1.2V

File:Sim 2 signal write SG13G2@1.2V.png

2026-09-01T16:14:27Z

Leviathan:

Sim 2 signal write SG13G2@1.2V

File:Sim 3 signal read hiz SG13G2@1.2V.png

2026-09-01T16:13:53Z

Leviathan:

Sim 3 signal read hiz SG13G2@1.2V

LibrePDK Padframe SPICE Verification Report SG13G2@1.2V

2026-09-01T16:12:50Z

Leviathan:

= LibrePDK Padframe SPICE Verification Report =

'''Technology:''' IHP SG13G2 (130nm BiCMOS)
'''Operating Voltage:''' 1.2 V
'''Verification Date:''' 2026-09-01 16:47:40 UTC
'''Extracted Netlist:''' <code>padframe.spice</code> (Magic VLSI Hierarchical Extraction)

== Executive Summary ==
{| class="wikitable" style="text-align:center; width:90%;"
! Test Scenario !! Target Net / Pad !! Measured Values !! Design Specification !! Status
|-
| style="text-align:left;" | '''ESD Clamping Transient''' || PAD_GPIO_0 (ESD Clamps) || Peak Clamped: 2.75 V || < 15.0 V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Output Drive (Write)''' || gpio_out_0 → PAD_GPIO_0 || Low: 0.00 V, High: 1.15 V || Rail-to-rail driver transition || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Input Sensing (Read / Hi-Z)''' || PAD_GPIO_1 → gpio_in_1 || Pad 0V → 0.00 V, Pad 1.2V → 1.15 V || Pad 0V -> Core > 0.8V, Pad 1.2V -> Core < 0.2V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Pad-to-Pad Dynamic Loopback''' || PAD_GPIO_0 → PAD_GPIO_1 || Bus: 0.12V / 1.20V | Rx: 0.00V / 1.15V || Full rail-to-rail dynamic loopback across frame || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|}

== Core Signal & Bonding Pad Interface Mapping ==
The LibrePDK padframe generator exposed unique net names defined in the JSON configuration for seamless Coriolis LEF/DEF digital core integration:

{| class="wikitable" style="width:90%; font-family:monospace;"
! Subcircuit Port Name !! Direction !! Interface Type !! Associated Physical Layer
|-
| '''VDD''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''VSS''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''gpio_in_0''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_0''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_0''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_0''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''gpio_in_1''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_1''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_1''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_1''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_miso_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_miso_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_miso_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MISO''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_cs_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_cs_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_cs_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_CS''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_tx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_tx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_tx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_TX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_rx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_rx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_rx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_RX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_sclk_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_sclk_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_sclk_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_SCLK''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_mosi_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_mosi_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_mosi_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MOSI''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|}

== Transient Simulation Waveforms ==

=== 1. ESD Clamping Event ===
Transient simulation applying a 2kV / 1.33A peak Human Body Model (HBM) current pulse directly to the bonding pad:
[[File:sim_1_esd_clamping.png|thumb|center|700px|ESD Diode and Rail Clamping Response under 1.33A Transient Current Pulse]]

=== 2. Digital Output Drive (Write) ===
Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:
[[File:sim_2_signal_write.png|thumb|center|700px|Signal Write: Core OUT driving Bonding Pad (0V to 1.2V)]]

=== 3. Digital Input Sensing (Read / Hi-Z) ===
External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:
[[File:sim_3_signal_read_hiz.png|thumb|center|700px|Signal Read: External Bonding Pad voltage sensed at Core IN]]

=== 4. Full Dynamic Loopback ===
End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):
[[File:Sim 4 pad to pad loopback SG13G2@1.2V.png|thumb|center|700px|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]

== Physical Verification & GDS Delivery ==
* '''GDSII Top Level:''' <code>padframe.raw.gds</code> / <code>padframe.gds</code>
* '''Magic Layout:''' <code>padframe.mag</code>
* '''SPICE Extracted Netlist:''' <code>padframe.spice</code>
* '''Simulation Models:''' <code>model.spice</code> / <code>design_header.ngspice</code>

[[index.php?title=Category:LibreSilicon Verification Reports]]
[[index.php?title=Category:LibrePDK]]
[[index.php?title=Category:SG13G2]]

LibrePDK Padframe SPICE Verification Report SG13G2@1.2V

2026-09-01T16:12:24Z

Leviathan:

= LibrePDK Padframe SPICE Verification Report =

'''Technology:''' IHP SG13G2 (130nm BiCMOS)
'''Operating Voltage:''' 1.2 V
'''Verification Date:''' 2026-09-01 16:47:40 UTC
'''Extracted Netlist:''' <code>padframe.spice</code> (Magic VLSI Hierarchical Extraction)

== Executive Summary ==
{| class="wikitable" style="text-align:center; width:90%;"
! Test Scenario !! Target Net / Pad !! Measured Values !! Design Specification !! Status
|-
| style="text-align:left;" | '''ESD Clamping Transient''' || PAD_GPIO_0 (ESD Clamps) || Peak Clamped: 2.75 V || < 15.0 V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Output Drive (Write)''' || gpio_out_0 → PAD_GPIO_0 || Low: 0.00 V, High: 1.15 V || Rail-to-rail driver transition || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Input Sensing (Read / Hi-Z)''' || PAD_GPIO_1 → gpio_in_1 || Pad 0V → 0.00 V, Pad 1.2V → 1.15 V || Pad 0V -> Core > 0.8V, Pad 1.2V -> Core < 0.2V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Pad-to-Pad Dynamic Loopback''' || PAD_GPIO_0 → PAD_GPIO_1 || Bus: 0.12V / 1.20V | Rx: 0.00V / 1.15V || Full rail-to-rail dynamic loopback across frame || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|}

== Core Signal & Bonding Pad Interface Mapping ==
The LibrePDK padframe generator exposed unique net names defined in the JSON configuration for seamless Coriolis LEF/DEF digital core integration:

{| class="wikitable" style="width:90%; font-family:monospace;"
! Subcircuit Port Name !! Direction !! Interface Type !! Associated Physical Layer
|-
| '''VDD''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''VSS''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''gpio_in_0''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_0''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_0''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_0''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''gpio_in_1''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_1''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_1''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_1''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_miso_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_miso_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_miso_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MISO''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_cs_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_cs_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_cs_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_CS''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_tx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_tx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_tx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_TX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_rx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_rx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_rx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_RX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_sclk_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_sclk_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_sclk_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_SCLK''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_mosi_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_mosi_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_mosi_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MOSI''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|}

== Transient Simulation Waveforms ==

=== 1. ESD Clamping Event ===
Transient simulation applying a 2kV / 1.33A peak Human Body Model (HBM) current pulse directly to the bonding pad:
[[File:sim_1_esd_clamping.png|thumb|center|700px|ESD Diode and Rail Clamping Response under 1.33A Transient Current Pulse]]

=== 2. Digital Output Drive (Write) ===
Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:
[[File:sim_2_signal_write.png|thumb|center|700px|Signal Write: Core OUT driving Bonding Pad (0V to 1.2V)]]

=== 3. Digital Input Sensing (Read / Hi-Z) ===
External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:
[[File:sim_3_signal_read_hiz.png|thumb|center|700px|Signal Read: External Bonding Pad voltage sensed at Core IN]]

=== 4. Full Dynamic Loopback ===
End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):
[[File:sim_4_pad_to_pad_loopback.png|thumb|center|700px|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]
[[File:Sim 4 pad to pad loopback SG13G2@1.2V.png|none|thumb]]

== Physical Verification & GDS Delivery ==
* '''GDSII Top Level:''' <code>padframe.raw.gds</code> / <code>padframe.gds</code>
* '''Magic Layout:''' <code>padframe.mag</code>
* '''SPICE Extracted Netlist:''' <code>padframe.spice</code>
* '''Simulation Models:''' <code>model.spice</code> / <code>design_header.ngspice</code>

[[index.php?title=Category:LibreSilicon Verification Reports]]
[[index.php?title=Category:LibrePDK]]
[[index.php?title=Category:SG13G2]]

File:Sim 4 pad to pad loopback SG13G2@1.2V.png

2026-09-01T16:10:08Z

Leviathan:

Sim 4 pad to pad loopback SG13G2@1.2V

LibrePDK Padframe SPICE Verification Report GF180A@3.3V

2026-09-01T16:08:57Z

Leviathan: Created page with "= LibrePDK Padframe SPICE Verification Report = '''Technology:''' IHP SG13G2 (130nm BiCMOS) '''Operating Voltage:''' 3.3 V '''Verification Date:''' 2026-09-01 16:01:45 UTC '''Extracted Netlist:''' <code>padframe.spice</code> (Magic VLSI Hierarchical Extraction) == Executive Summary == {| class="wikitable" style="text-align:center; width:90%;" ! Test Scenario !! Target Net / Pad !! Measured Values !! Design Specification !! Status |- | style="text-align:left;" |..."

= LibrePDK Padframe SPICE Verification Report =

'''Technology:''' IHP SG13G2 (130nm BiCMOS)
'''Operating Voltage:''' 3.3 V
'''Verification Date:''' 2026-09-01 16:01:45 UTC
'''Extracted Netlist:''' <code>padframe.spice</code> (Magic VLSI Hierarchical Extraction)

== Executive Summary ==
{| class="wikitable" style="text-align:center; width:90%;"
! Test Scenario !! Target Net / Pad !! Measured Values !! Design Specification !! Status
|-
| style="text-align:left;" | '''ESD Clamping Transient''' || PAD_GPIO_0 (ESD Clamps) || Peak Clamped: 4.30 V || < 15.0 V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Output Drive (Write)''' || gpio_out_0 → PAD_GPIO_0 || Low: 2.84 V, High: 0.65 V || Rail-to-rail driver transition || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Input Sensing (Read / Hi-Z)''' || PAD_GPIO_1 → gpio_in_1 || Pad 0V → 0.00 V, Pad 3.3V → 2.87 V || Pad 0V -> Core > 0.8V, Pad 3.3V -> Core < 0.2V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Pad-to-Pad Dynamic Loopback''' || PAD_GPIO_0 → PAD_GPIO_1 || Bus: 1.40V / 1.37V | Rx: 2.85V / -0.01V || Full rail-to-rail dynamic loopback across frame || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|}

== Core Signal & Bonding Pad Interface Mapping ==
The LibrePDK padframe generator exposed unique net names defined in the JSON configuration for seamless Coriolis LEF/DEF digital core integration:

{| class="wikitable" style="width:90%; font-family:monospace;"
! Subcircuit Port Name !! Direction !! Interface Type !! Associated Physical Layer
|-
| '''VDD''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''VSS''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''gpio_in_0''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_0''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_0''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_0''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''gpio_in_1''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_1''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_1''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_1''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_miso_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_miso_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_miso_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MISO''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_cs_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_cs_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_cs_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_CS''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_tx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_tx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_tx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_TX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_rx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_rx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_rx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_RX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_sclk_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_sclk_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_sclk_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_SCLK''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_mosi_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_mosi_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_mosi_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MOSI''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|}

== Transient Simulation Waveforms ==

=== 1. ESD Clamping Event ===
Transient simulation applying a 2kV / 1.33A peak Human Body Model (HBM) current pulse directly to the bonding pad:
[[File:sim_1_esd_clamping.png|thumb|center|700px|ESD Diode and Rail Clamping Response under 1.33A Transient Current Pulse]]

=== 2. Digital Output Drive (Write) ===
Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:
[[File:sim_2_signal_write.png|thumb|center|700px|Signal Write: Core OUT driving Bonding Pad (0V to 3.3V)]]

=== 3. Digital Input Sensing (Read / Hi-Z) ===
External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:
[[File:sim_3_signal_read_hiz.png|thumb|center|700px|Signal Read: External Bonding Pad voltage sensed at Core IN]]

=== 4. Full Dynamic Loopback ===
End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):
[[File:sim_4_pad_to_pad_loopback.png|thumb|center|700px|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]

== Physical Verification & GDS Delivery ==
* '''GDSII Top Level:''' <code>padframe.raw.gds</code> / <code>padframe.gds</code>
* '''Magic Layout:''' <code>padframe.mag</code>
* '''SPICE Extracted Netlist:''' <code>padframe.spice</code>
* '''Simulation Models:''' <code>model.spice</code> / <code>design_header.ngspice</code>

[[Category:LibreSilicon Verification Reports]]
[[Category:LibrePDK]]
[[Category:SG13G2]]

LibrePDK Padframe SPICE Verification Report SG13G2@1.2V

2026-09-01T16:08:24Z

Leviathan: Created page with "= LibrePDK Padframe SPICE Verification Report = '''Technology:''' IHP SG13G2 (130nm BiCMOS) '''Operating Voltage:''' 1.2 V '''Verification Date:''' 2026-09-01 16:47:40 UTC '''Extracted Netlist:''' <code>padframe.spice</code> (Magic VLSI Hierarchical Extraction) == Executive Summary == {| class="wikitable" style="text-align:center; width:90%;" ! Test Scenario !! Target Net / Pad !! Measured Values !! Design Specification !! Status |- | style="text-align:left;" |..."

= LibrePDK Padframe SPICE Verification Report =

'''Technology:''' IHP SG13G2 (130nm BiCMOS)
'''Operating Voltage:''' 1.2 V
'''Verification Date:''' 2026-09-01 16:47:40 UTC
'''Extracted Netlist:''' <code>padframe.spice</code> (Magic VLSI Hierarchical Extraction)

== Executive Summary ==
{| class="wikitable" style="text-align:center; width:90%;"
! Test Scenario !! Target Net / Pad !! Measured Values !! Design Specification !! Status
|-
| style="text-align:left;" | '''ESD Clamping Transient''' || PAD_GPIO_0 (ESD Clamps) || Peak Clamped: 2.75 V || < 15.0 V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Output Drive (Write)''' || gpio_out_0 → PAD_GPIO_0 || Low: 0.00 V, High: 1.15 V || Rail-to-rail driver transition || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Input Sensing (Read / Hi-Z)''' || PAD_GPIO_1 → gpio_in_1 || Pad 0V → 0.00 V, Pad 1.2V → 1.15 V || Pad 0V -> Core > 0.8V, Pad 1.2V -> Core < 0.2V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Pad-to-Pad Dynamic Loopback''' || PAD_GPIO_0 → PAD_GPIO_1 || Bus: 0.12V / 1.20V | Rx: 0.00V / 1.15V || Full rail-to-rail dynamic loopback across frame || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|}

== Core Signal & Bonding Pad Interface Mapping ==
The LibrePDK padframe generator exposed unique net names defined in the JSON configuration for seamless Coriolis LEF/DEF digital core integration:

{| class="wikitable" style="width:90%; font-family:monospace;"
! Subcircuit Port Name !! Direction !! Interface Type !! Associated Physical Layer
|-
| '''VDD''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''VSS''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''gpio_in_0''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_0''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_0''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_0''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''gpio_in_1''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_1''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_1''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_1''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_miso_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_miso_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_miso_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MISO''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_cs_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_cs_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_cs_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_CS''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_tx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_tx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_tx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_TX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_rx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_rx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_rx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_RX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_sclk_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_sclk_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_sclk_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_SCLK''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_mosi_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_mosi_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_mosi_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MOSI''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|}

== Transient Simulation Waveforms ==

=== 1. ESD Clamping Event ===
Transient simulation applying a 2kV / 1.33A peak Human Body Model (HBM) current pulse directly to the bonding pad:
[[File:sim_1_esd_clamping.png|thumb|center|700px|ESD Diode and Rail Clamping Response under 1.33A Transient Current Pulse]]

=== 2. Digital Output Drive (Write) ===
Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:
[[File:sim_2_signal_write.png|thumb|center|700px|Signal Write: Core OUT driving Bonding Pad (0V to 1.2V)]]

=== 3. Digital Input Sensing (Read / Hi-Z) ===
External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:
[[File:sim_3_signal_read_hiz.png|thumb|center|700px|Signal Read: External Bonding Pad voltage sensed at Core IN]]

=== 4. Full Dynamic Loopback ===
End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):
[[File:sim_4_pad_to_pad_loopback.png|thumb|center|700px|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]

== Physical Verification & GDS Delivery ==
* '''GDSII Top Level:''' <code>padframe.raw.gds</code> / <code>padframe.gds</code>
* '''Magic Layout:''' <code>padframe.mag</code>
* '''SPICE Extracted Netlist:''' <code>padframe.spice</code>
* '''Simulation Models:''' <code>model.spice</code> / <code>design_header.ngspice</code>

[[Category:LibreSilicon Verification Reports]]
[[Category:LibrePDK]]
[[Category:SG13G2]]

Pad Frame Generator

2026-09-01T16:07:08Z

Leviathan:

[[File:Padframe Example.png|thumb|Example of a pad frame for SG13G2@1.2V]]
The Pad Frame Generator is part of the [[LibrePDK]] and provides the [[Pad Cell Generator]] functionality.

It's job is to assemble a ready to use pad frame harness, with ESD protection and power rail wire width properly adjusted for accommodating the intended current driving capacity as well as the intended voltage levels to be used.

== Types of Pad Cells produced ==
Currently we support only simple IO [[Pad Cell]], analog cells, and power cells, complex pad cells still are being in development.

The very special impedance compensated pad cell in the works ([[High-Speed Impedance-Compensated Pad Cell]]) is needed in order to hook up DDR4 RAM to our chips or build a PCIe device.

== How to use ==
There are two options on how you can run the Pad Frame Generator on your machine, you can go the easy route and use a docker container or you can [[Pad Frame Generator#Installation|set up LibrePDK locally]].

An example for a paframe config can be found here [https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/tests/padframes/padframe_sg13g2_1v2.json?ref_type=heads padframe_sg13g2_1v2.json]

=== Docker ===
First pull the docker image for the [[LibrePDK]] in order to make sure the image is up to date by running<syntaxhighlight lang="bash">
docker pull leviathanch/librepdk:latest
</syntaxhighlight>Then you can feed your JSON config for the padframe you have configured to the pad frame generator script contained in the docker image.

<syntaxhighlight lang="bash">docker run -it --rm \
-e HOST_UID=$(id -u) -e HOST_GID=$(id -g) \
-v "$(pwd)":/workspace leviathanch/librepdk:latest \
librepdk_padframe_generator -i padframe_config.json \
-o my_padframe</syntaxhighlight>After running the generator you should have a folder named my_padframe containing the LEF, DEF, Magic and all the other files you need for running a full synthesis flow of your designs.

=== Run Locally ===
After [[Pad Frame Generator#Installation|seting up LibrePDK locally]] you can generate your pad frame by running<syntaxhighlight lang="bash">uv run \
librepdk_padframe_generator -i padframe_config.json \
-o my_padframe</syntaxhighlight>

== Test cases ==
Tests have been performed for the sample pad frame configurations for [https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/tests/padframes/padframe_gf180a_3v3.json?ref_type=heads IHP's SG13G2 at 1.2V] and the [https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/tests/padframes/padframe_gf180a_3v3.json?ref_type=heads GF180A process at 3.3V] (by Global Foundries).

Please look at [[LibrePDK Padframe SPICE Verification Report SG13G2@1.2V]] and [[LibrePDK Padframe SPICE Verification Report GF180A@3.3V]] for the simulation verification results and wave forms.

== Installation ==
Since the Pad Frame Generator is part of [[LibrePDK]] you can find the guide on how to install all the dependencies in the [[LibrePDK#Installation|Installation section of the LibrePDK]] page

== Benchmarks ==
Generating all those individual geometries takes a lot of time, an initial generation run can take up to half an hour due to the complexity and size of a pad frame and its pad cells, which is why we introduced component caching.

=== Initial run ===
The initial run for GF180A takes around 20 minutes, IHP and Skywater with even more layers can take up to 32 minutes<syntaxhighlight lang="bash">
real 20m48.886s
user 20m46.885s
sys 0m3.880s
</syntaxhighlight>

=== Further runs ===
During the second run that generation time is cut in half when assembling the padframe and writing it out.<syntaxhighlight lang="bash">
real 8m43.972s
user 8m40.889s
sys 0m4.139s
</syntaxhighlight>

Pad Frame Generator

2026-08-31T16:00:32Z

Leviathan: /* How to use */

[[File:Padframe Example.png|thumb|Example of a pad frame for SG13G2@1.2V]]
The Pad Frame Generator is part of the [[LibrePDK]] and provides the [[Pad Cell Generator]] functionality.

It's job is to assemble a ready to use pad frame harness, with ESD protection and power rail wire width properly adjusted for accommodating the intended current driving capacity as well as the intended voltage levels to be used.

== Types of Pad Cells produced ==
Currently we support only simple IO [[Pad Cell]], analog cells, and power cells, complex pad cells still are being in development.

The very special impedance compensated pad cell in the works ([[High-Speed Impedance-Compensated Pad Cell]]) is needed in order to hook up DDR4 RAM to our chips or build a PCIe device.

== How to use ==
There are two options on how you can run the Pad Frame Generator on your machine, you can go the easy route and use a docker container or you can [[Pad Frame Generator#Installation|set up LibrePDK locally]].

An example for a paframe config can be found here [https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/tests/padframes/padframe_sg13g2_1v2.json?ref_type=heads padframe_sg13g2_1v2.json]

=== Docker ===
First pull the docker image for the [[LibrePDK]] in order to make sure the image is up to date by running<syntaxhighlight lang="bash">
docker pull leviathanch/librepdk:latest
</syntaxhighlight>Then you can feed your JSON config for the padframe you have configured to the pad frame generator script contained in the docker image.

<syntaxhighlight lang="bash">docker run -it --rm \
-e HOST_UID=$(id -u) -e HOST_GID=$(id -g) \
-v "$(pwd)":/workspace leviathanch/librepdk:latest \
librepdk_padframe_generator -i padframe_config.json \
-o my_padframe</syntaxhighlight>After running the generator you should have a folder named my_padframe containing the LEF, DEF, Magic and all the other files you need for running a full synthesis flow of your designs.

=== Run Locally ===
After [[Pad Frame Generator#Installation|seting up LibrePDK locally]] you can generate your pad frame by running<syntaxhighlight lang="bash">uv run \
librepdk_padframe_generator -i padframe_config.json \
-o my_padframe</syntaxhighlight>
== Installation ==
Since the Pad Frame Generator is part of [[LibrePDK]] you can find the guide on how to install all the dependencies in the [[LibrePDK#Installation|Installation section of the LibrePDK]] page

== Benchmarks ==
Generating all those individual geometries takes a lot of time, an initial generation run can take up to half an hour due to the complexity and size of a pad frame and its pad cells, which is why we introduced component caching.

=== Initial run ===
The initial run for GF180A takes around 20 minutes, IHP and Skywater with even more layers can take up to 32 minutes<syntaxhighlight lang="bash">
real 20m48.886s
user 20m46.885s
sys 0m3.880s
</syntaxhighlight>

=== Further runs ===
During the second run that generation time is cut in half when assembling the padframe and writing it out.<syntaxhighlight lang="bash">
real 8m43.972s
user 8m40.889s
sys 0m4.139s
</syntaxhighlight>

Pad Frame Generator

2026-08-31T15:58:52Z

Leviathan: /* How to use */

Pad Frame Generator

2026-08-31T13:38:54Z

Leviathan: /* How to use */

Pad Frame Generator

2026-08-31T13:38:26Z

Leviathan: /* Types of Pad Cells produced */

Pad Frame Generator

2026-08-31T13:38:14Z

Leviathan: /* How to use */

Pad Frame Generator

2026-08-31T13:37:38Z

Leviathan: /* How to use */

Pad Frame Generator

2026-08-31T13:20:36Z

Leviathan: /* Benchmarks */

LibreSilicon stack

2026-08-31T08:26:20Z

Leviathan: /* Pad Frames */

LibreSilicon includes not only software but also a manufacturing process flow standard with recipes and machine designs.
A detailed overview with links goes onto this page.

LibreSilicon can be roughly divided into two main categories, physical manufacturing as well as the tool chain part

== Software ==
For doing anything useful with your foundry, you need a way of verifying your setup, for which we provide you the test wafer generator [[Danube River]], then you need standard logic cells for synthesizing, placing and routing your layout, and of pad cells so that you can wire bond your chip;

=== Process Verification ===
When setting up a new foundry, no matter the scale, the physical manufacturing needs to be verified, using a test wafer, for this purpose we provide a dynamic test wafer generator named [[Danube River]], which you can provide your own technology specs based on initial calculations for your setup and then verify and adjust your values until everything is correct.
[[File:Danube For New Foundry.png|none|thumb|653x653px]]

=== Standard Cells ===
You need standard logic cells, small logic gate layouts made from place and routing discrete FETs, in order to turn the RTL level logic Yosys spits out into an actual digital chip layout.

You can now use the [[LibreStandardCell]] generator and generate custom standard logic cell libraries where you decide the target technology, voltage, height and thermal budget.
[[File:LibreStandardCell screeny2.png|none|thumb]]
Originally Philip was working on [[StdCellLib]], but he re-licensed it under Apache which kind of defeats the purpose of a project calling itself '''Libre'''Silicon. Because Leviathan was a bit triggered by this due to his definition of Libre being the same as the Free Software Foundation, which means, that it's supposed under a GNU Public License, he decided to work on introducing the functionality for placing and routing standard logic cells in [[LibrePDK]] as well, in addition to analog and pad cell generation.

=== Pad Cells ===
The [[Pad Cell Generator]] is part of the [[LibrePDK]] and can be used to created custom sets of pad cells with custom rail voltages and you can even define a set of currents your pad frame is supposed to end up driving.
[[File:Sg13g2 1v2 io cell 60mA 1p2V.png|none|thumb|padframe_sg13g2_1v2/io_cell_60mA_1p2V/]]
The pad cell has such thin wires, because the ultimate wire width has to be determined based on the final current which is supposed to be driven by the overall pad frame the cells are being generated for.
=== Pad Frames ===
The [[Pad Frame Generator]] has the job of taking in a JSON with pin assignment for the East, North, South and West bank and then calculate the wire dimensions of the overall padframe based on the projected peak currents as well as to choose the right pad cell type for each assigned pin.
[[File:Padframe Example.png|none|thumb|Pad Frame Example SG13G2@1.2V]]
The resulting output will be a pad frame in Magic, GDS2, LEF and DEF format, which you can use for placing and routing your internal logic to.

==Physical manufacturing==

The physical manufacturing includes things like:

* [[Chemical processing]]
* [[Photolithography]]

LibreSilicon stack

2026-08-31T08:17:10Z

Leviathan: /* Pad Cells */

LibreSilicon includes not only software but also a manufacturing process flow standard with recipes and machine designs.
A detailed overview with links goes onto this page.

LibreSilicon can be roughly divided into two main categories, physical manufacturing as well as the tool chain part

== Software ==
For doing anything useful with your foundry, you need a way of verifying your setup, for which we provide you the test wafer generator [[Danube River]], then you need standard logic cells for synthesizing, placing and routing your layout, and of pad cells so that you can wire bond your chip;

=== Process Verification ===
When setting up a new foundry, no matter the scale, the physical manufacturing needs to be verified, using a test wafer, for this purpose we provide a dynamic test wafer generator named [[Danube River]], which you can provide your own technology specs based on initial calculations for your setup and then verify and adjust your values until everything is correct.
[[File:Danube For New Foundry.png|none|thumb|653x653px]]

=== Standard Cells ===
You need standard logic cells, small logic gate layouts made from place and routing discrete FETs, in order to turn the RTL level logic Yosys spits out into an actual digital chip layout.

You can now use the [[LibreStandardCell]] generator and generate custom standard logic cell libraries where you decide the target technology, voltage, height and thermal budget.
[[File:LibreStandardCell screeny2.png|none|thumb]]
Originally Philip was working on [[StdCellLib]], but he re-licensed it under Apache which kind of defeats the purpose of a project calling itself '''Libre'''Silicon. Because Leviathan was a bit triggered by this due to his definition of Libre being the same as the Free Software Foundation, which means, that it's supposed under a GNU Public License, he decided to work on introducing the functionality for placing and routing standard logic cells in [[LibrePDK]] as well, in addition to analog and pad cell generation.

=== Pad Cells ===
The [[Pad Cell Generator]] is part of the [[LibrePDK]] and can be used to created custom sets of pad cells with custom rail voltages and you can even define a set of currents your pad frame is supposed to end up driving.
[[File:Sg13g2 1v2 io cell 60mA 1p2V.png|none|thumb|padframe_sg13g2_1v2/io_cell_60mA_1p2V/]]
The pad cell has such thin wires, because the ultimate wire width has to be determined based on the final current which is supposed to be driven by the overall pad frame the cells are being generated for.
=== Pad Frames ===
The [[Pad Frame Generator]] has the job of taking in a JSON with pin assignment for the East, North, South and West bank and then calculate the wire dimensions of the overall padframe based on the projected peak currents as well as to choose the right pad cell type for each assigned pin.
[[File:Pad Frame v2 Example SG13G2@1V2.png|none|thumb|Pad Frame Example SG13G2@1.2V]]
The resulting output will be a pad frame in Magic, GDS2, LEF and DEF format, which you can use for placing and routing your internal logic to.

==Physical manufacturing==

The physical manufacturing includes things like:

* [[Chemical processing]]
* [[Photolithography]]

File:Sg13g2 1v2 io cell 60mA 1p2V.png

2026-08-31T08:16:44Z

Leviathan:

padframe_sg13g2_1v2/io_cell_60mA_1p2V/

High-Speed Impedance-Compensated Pad Cell

2026-08-19T06:53:48Z

Leviathan: /* 4.4 Pad Capacitance () and ESD Constraints */

= High-Speed Impedance-Compensated Pad Cell Architecture & Specification =
'''Document Status:''' Draft / Initial Specification

'''Target Process:''' LibrePDK (IHP SG13G2 / Generic CMOS)

'''Target Applications:''' High-Speed Interfaces (DDR4 SSTL/POD, PCIe Gen 1–3, High-Speed GPIO)
== 1. Overview & Problem Statement ==
Standard single-stage push-pull digital I/O drivers (consisting of a single large PMOS and NMOS transistor pair) are strictly insufficient for high-speed transmission lines ( single-ended or differential).

Uncompensated drivers suffer from severe non-linearities:

'''Impedance Mismatch & Reflections:''' Driver output impedance varies drastically across Process, Voltage, and Temperature (PVT) corners. Unmatched termination causes destructive signal reflections, ringing, and inter-symbol interference (ISI).

'''Lack of Dynamic Termination:''' Receiver modes require active On-Die Termination (ODT) to absorb incoming wave fronts without requiring discrete PCB resistors.

'''Lack of Drive-Strength Control:''' Variable trace lengths on PCBs require programmable output impedance to match line characteristics (, , , , , ).

To resolve these physical limitations, the next-generation LibreSilicon I/O library must move from static digital drivers to Segmented, PVT-Calibrated Output Drivers with Integrated ODT.
== 2. Core Architectural Pillars ==
An impedance-compensated pad cell consists of three mandatory functional subsystems:
[[File:Cell Corridor Macro.png|thumb|center|800px|High-Level Block Diagram of Calibrated Pad Cell Subsystem]]
=== 2.1 Multi-Leg / Segmented Output Driver ===
Rather than a single monolithic transistor, the output driver array is divided into parallel driver legs (typically to ).

Each leg consists of a pull-up PMOS and pull-down NMOS in series with a precision poly-silicon resistor.

Leg parameters are sized such that the total leg resistance satisfies:

Enabling combinations of parallel legs provides discrete target output impedances:

{| class="wikitable"
|+ Output Impedance Selection
! Enabled Legs !! Effective Driver Impedance !! Application Target
|-
| 1 || || High-impedance termination leg / Low-power drive
|-
| 2 || || ODT Receiver Mode (DDR4 half-strength)
|-
| 4 || || Standard PCB Line Match
|-
| 5 || || DDR4 Nominal Output Impedance
|-
| 7 || || High-drive / PCIe Nominal Output
|}
=== 2.2 On-Die Termination (ODT) Logic ===
When operating as a receiver, the driver logic overrides normal push-pull operation. The pre-driver controls enable both the PMOS pull-up and NMOS pull-down legs simultaneously to form a center-tapped Thevenin equivalent termination or pull-up termination (e.g., POD12 for DDR4) matched to the trace impedance .
=== 2.3 ZQ Calibration Engine (PVT Compensation) ===
Because silicon fabrication tolerances, operating temperature, and fluctuations alter and by up to , dynamic digital calibration is required:

An external precision resistor is tied to a dedicated '''ZQ Pad'''.

An internal state machine (using an analog comparator and SAR or Up/Down counter) adjusts binary weighted calibration vectors (CAL_PCODE[N:0] and CAL_NCODE[N:0]).

The calibrated code vectors are distributed to all I/O pads across the die to trim active slice widths continuously.

== 3. Pre-Driver & Driver Netlist Topology (JSON) ==
To support automated Place & Route (PnR) inside LibreSilicon, the single-channel gate output format must be refactored into a segmented pre-driver slice array (driver_logic_segmented).

This is just a draft, we still have to re-introduce complex sub-components in [[LibrePDK]]

=== Segmented Driver Logic ===
The JSON netlist for the segmented driver logic can be found here: https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/designs/driver_logic_segmented.json?ref_type=heads

=== Pre-Drive Slice ===
The JSON netlist for the preslice can be found here: https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/designs/predriver_slice.json?ref_type=heads
[[File:Predriver slice schematic.png|none|thumb|800x800px|Preslice Schematic]]

=== Predriver Slice Logic Specification ===
The pre-driver slice controls individual driver leg segments. It evaluates calibration bits (<tt>BIT_CAL_P</tt>, <tt>BIT_CAL_N</tt>), global tri-state enable (<tt>GLOBAL_EN</tt>), and On-Die Termination override (<tt>ODT_EN</tt>) to drive the gates of the output stage (<tt>GATE_P</tt> and <tt>GATE_N</tt>).

{| class="wikitable"
|+ Logic Table for predriver_slice
|-
! colspan="5" | Inputs !! colspan="2" | Outputs
|-
! DATA_IN !! GLOBAL_EN !! ODT_EN !! BIT_CAL_P !! BIT_CAL_N !! GATE_P !! GATE_N
|-
| 0 || 0 || 0 || 0 || 0 || Z || Z
|-
| 0 || 0 || 0 || 0 || 1 || Z || Z
|-
| 0 || 0 || 0 || 1 || 0 || 0 || 0
|-
| 0 || 0 || 0 || 1 || 1 || 0 || 0
|-
| 0 || 0 || 1 || 0 || 0 || Z || Z
|-
| 0 || 0 || 1 || 0 || 1 || 1 || 0
|-
| 0 || 0 || 1 || 1 || 0 || Z || Z
|-
| 0 || 0 || 1 || 1 || 1 || 0 || 0
|-
| 0 || 1 || 0 || 0 || 0 || 0 || 0
|-
| 0 || 1 || 0 || 0 || 1 || 0 || 0
|-
| 0 || 1 || 0 || 1 || 0 || 0 || 0
|-
| 0 || 1 || 0 || 1 || 1 || 0 || 0
|-
| 0 || 1 || 1 || 0 || 0 || Z || Z
|-
| 0 || 1 || 1 || 0 || 1 || Z || Z
|-
| 0 || 1 || 1 || 1 || 0 || Z || Z
|-
| 0 || 1 || 1 || 1 || 1 || 0 || 0
|-
| 1 || 0 || 0 || 0 || 0 || Z || Z
|-
| 1 || 0 || 0 || 0 || 1 || 0 || 0
|-
| 1 || 0 || 0 || 1 || 0 || Z || Z
|-
| 1 || 0 || 0 || 1 || 1 || 0 || 0
|-
| 1 || 0 || 1 || 0 || 0 || Z || Z
|-
| 1 || 0 || 1 || 0 || 1 || Z || Z
|-
| 1 || 0 || 1 || 1 || 0 || 0 || 1
|-
| 1 || 0 || 1 || 1 || 1 || 0 || 0
|-
| 1 || 1 || 0 || 0 || 0 || 0 || 0
|-
| 1 || 1 || 0 || 0 || 1 || 0 || 0
|-
| 1 || 1 || 0 || 1 || 0 || 0 || 0
|-
| 1 || 1 || 0 || 1 || 1 || 0 || 0
|-
| 1 || 1 || 1 || 0 || 0 || Z || Z
|-
| 1 || 1 || 1 || 0 || 1 || Z || Z
|-
| 1 || 1 || 1 || 1 || 0 || Z || Z
|-
| 1 || 1 || 1 || 1 || 1 || 0 || 0
|}
==== Mode Functional Descriptions ====
* '''Disabled / Uncalibrated:''' When calibration code bits are low, the slice is fully isolated from the output pad, preventing uncalibrated drive strength contributions.
* '''Active Drive:''' Normal push-pull switching mode when <tt>GLOBAL_EN</tt> is asserted and <tt>ODT_EN</tt> is deasserted.
* '''On-Die Termination (ODT):''' Asserts both pull-up (<tt>GATE_P=0</tt>) and pull-down (<tt>GATE_N=1</tt>) networks simultaneously, forming a center-tapped Thevenin termination load ($R_{\text{eq}} = Z_0$) at the pad.

== 4. LibrePDK Physical Layout & Silicon Process Rules ==
When laying out the physical pad cell in LibrePDK, engineers must adhere to four strict silicon process guidelines:
=== 4.1 Integrated Poly Resistors ===
Do NOT rely exclusively on transistor channel resistance for matching. Transistor channel resistance is non-linear with respect to drain-source voltage .

Place STI-isolated poly resistors in series with transistor drains to linearize the driver output impedance curve.
Ensure consumes to of total leg impedance ( poly resistor + FET ).
=== 4.2 Metal Routing Congestion & Layer Budget ===
'''Metal Layer Allocation:''' Simple digital pads use and . Segmented drivers routing 8–16 gate signals (PMOS_OUT[N], NMOS_OUT[N]) and calibration control buses MUST utilize (and where available).

Set "max_signal_metal": 3 in PnR configurations to prevent shorting routing tracks across standard cells.
=== 4.3 Slew Rate Mismatch & Skew Control ===
Asymmetrical routing from the pre-driver data input OUT to individual leg slices creates switching skew between driver branches.

Inter-leg skew induces severe dynamic impedance transients and timing jitter during high-speed signal transitions.

'''Requirement:''' The Place & Route engine must enforce symmetric -tree routing for signal paths into LEG_0_PREDRV through LEG_N_PREDRV.
=== 4.4 Pad Capacitance and ESD Constraints ===
Paralleling multiple driver transistors increases total junction capacitance on the output pad pin.

Excessive degrades high-frequency edge rates.

Ensure pad layout uses multi-finger folded transitors placed in close proximity to ESD diodes to minimize parasitic substrate capacitance.
== 5. Implementation Roadmap for LibreSilicon Team ==
'''Step 1: Standardize predriver_slice Sub-Macro'''

Design and simulate the NOR/NAND gating matrix for a single pre-driver slice with ODT enable override.

'''Step 2: Poly Resistor Characterization'''

Extract exact sheet resistance for poly silicon layer in IHP SG13G2 / LibrePDK to dimension the base leg.

'''Step 3: ZQ Calibration State Machine Netlist'''

Construct a centralized ZQ controller cell to generate CAL_PCODE and CAL_NCODE vectors across the IO ring.

'''Step 4: SPICE Corner Analysis'''

Run transient SPICE simulations across TT, FF, and SS process corners to verify output impedance holding tolerance within of target .

LibrePDK

2026-08-15T22:06:12Z

Leviathan: /* Ubuntu */

The LibrePDK is the library driving [[Danube River]] and the [[Pad Cell Generator]]
[[File:LibrePDK.png|none|thumb|695x695px|ALibrePDK screen shot]]
It is responsible for generating discrete parts with specific parameters for a specific process.

The properties of the parts can be optimized by utilizing the calibration values extracted from the measurements of taped out Danube River test wafers.

== Adding a new technology ==
Technologies currently supported can be found in the technologies subfolder.

https://gitlab.libresilicon.com/generator-tools/librepdk/-/tree/master/LibrePDK/technologies?ref_type=heads

New technologies can be added by modifying '''scripts/update_technologies.sh''' and adding a tech.python script to the technologies folder.

After that, LibrePDK should be capable of auto discovering the new process after running the update script.

== Dependencies ==

=== Ubuntu ===
We are using Ubuntu 25.04 in our Docker containers

Simply run<syntaxhighlight lang="bash">apt-get update && apt-get install -y --no-install-recommends \
autoconf automake bash bison build-essential ca-certificates cargo checkinstall clang cmake \
curl flex g++ gcc git git-lfs glpk-utils gosu imagemagick libblas-dev libcairo2-dev \
libcurl4-gnutls-dev libeigen3-dev libfl-dev libgit2-dev libgit2-glib-1.0-dev libglpk-dev \
libglu1-mesa-dev liblemon-dev libreadline-dev libsparsehash-dev libsqlite3-dev libtool \
libxaw7-dev libz-dev llvm make mmv pdf2svg pkg-config python3-dev python3-full python3-pip \
rsync ruby ruby-dev rustc software-properties-common sqlite3 sudo tcl tcl8.6-dev tcllib \
texlive-latex-recommended time tk8.6-dev tklib unzip vim wget z3 zlib1g-dev
</syntaxhighlight>

=== Boost ===
In order for [[LibrePDK#Limbo|Limbo]] to successfully compile we need to install Boost.

We are currently using boost 1.91.0, of which the tar ball can be obtained here https://archives.boost.io/release/1.91.0/source/boost_1_91_0.tar.gz

With the following command Boost can be installed quickly<syntaxhighlight lang="bash">
./bootstrap.sh \
--prefix=/usr \
--with-python-version=3.13

./b2 install
</syntaxhighlight>Note that the Python version we compile boost for is 3.13, because LibrePDK hasn't been tested with any later version.

=== ngspice ===
For the simulation and characterization of standard cells you will need the ngspice frontend and backend library

Currently we are using version 44.2 of ngspice, the tar ball can be obtained from here: https://download.industrysoftware.automation.siemens.com/open-source/ngspice-44.2.tar.gz

==== Backend configuration ====
The backend library is needed for Charlib in order to run characterization of our cells<syntaxhighlight lang="bash">
./autogen.sh
./configure --with-ngshared --enable-xspice --enable-cider --enable-openmp --disable-debug
make -j$(nproc)
make install

</syntaxhighlight>After compilation and installation you should have a libngspice.so in your ldpath which charlib can pick up on and load it.

==== Frontend configuration ====
This will compile and install the ngspice CLI binary which is needed when you wanna simulate your circuits.<syntaxhighlight lang="bash">
./autogen.sh
../configure --with-x --with-readline=yes --enable-xspice
make -j$(nproc)
make install

</syntaxhighlight>ngspice is also used when loading and importing new technologies into LibrePDK

=== OpenVAF models ===
IHP's SG13G2 technology node uses OpenVAF models for the ngspice simulation tool.

The following script will make sure that rust and the OpenVAF tool are present and then
compiles the models into the osdi format and places them into the technology directory
ready to be used by LibrePDK.

Simply run the following script and confirm the installation by checking for the LibrePDK/technologies/spice/SG13G2/devices/*/*.osdi files.

This requires the LibrePDK repo to already have [[LibrePDK#Installation|been cloned and updated]] as shown in.

./scripts/update_ngspice_extensions.sh

=== LP solver ===

Google now officially runs the project and you can get the most recent version from GitHub

Install is by cloning and building it<syntaxhighlight lang="bash">
git clone https://github.com/lp-solve/lp_solve
pushd lp_solve/lpsolve55
rm -rf bin/ux64
sh ccc
popd
</syntaxhighlight> Then you can copy the shared object file in solve/lpsolve55/bin/ux64 into your /usr/lib64 and copy the headers with<syntaxhighlight lang="bash">
mkdir /usr/include/lpsolve
cp lp_solve/*.h /usr/include/lpsolve/
</syntaxhighlight>OR, you can install the system package and devel package with your package manager

=== Lemon ===

That library has been developed by a Hungarian university which doesn't maintain their Mercurial setup. Best approach is to use the version you find in your distribution
=== Limbo ===

The official version of Limbo has been a total mess when it comes to building libs and linking them. I had to make some severe modifications which makes CMake properly build shared object files and detects the system wide installation of the dependencies
using proper CMake detection functions

Just run<syntaxhighlight lang="bash">
git clone https://gitlab.libresilicon.com/leviathan/limbo.git
mkdir Limbo/build
pushd Limbo/build
cmake ..
make
make install
popd
</syntaxhighlight>
== Installation ==
Before you start installing LibrePDK, you first need to [[LibrePDK#Dependencies|install its dependencies]] so that its C++ extensions and other C++ tools compile successfully.

After that, please clone the repo.

pip install [https://gitlab.libresilicon.com/generator-tools/librepdk.git https+git://gitlab.libresilicon.com/generator-tools/librepdk.git]

Don't forget to make sure that all the submodules and their submodules are cloned

git submodule update --init --recursive

For placement of discrete componentes used in more complex components like Driver Circuits, OpAmps, etc. IdeaPlaceExPy is being used.

IdeaPlaceExPy requires the Python system headers to be installed and the virtual env has to match the Python version with which it was compiled.

=== Using LibrePDK in a Virtual Environment (FINAL SETUP) ===
It is recommended to use LibrePDK in a Python virtual environment to avoid dependency conflicts with
system-wide Python packages.

After you've installed all the below dependencies the recommended way of installing the remaining dependencies is to run<syntaxhighlight lang="bash">
uv sync --no-cache
</syntaxhighlight>

== Building your own Docker images ==
Inside of the LibrePDK source folder you will find a script where you can uncomment and comment specific build stages of the multistage Docker build covering all the dependencies

Check out the script '''[https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/scripts/build_docker_images.sh?ref_type=heads scripts/build_docker_images.sh]'''

= Components =
LibrePDK provides generators for the basic components usually found within a VLSI/ULSI design, such as resistors, capacitors, diodes and transistors.

== Capacitors ==
LibrePDK can calculate the specific geometry based on the device rules and available parameters for generating any desired target capacitance value. Below a 50pF capacitor can be seen. You will notice the enormous dimensions of the structure.
[[File:50pF MiMCap (GF180A, 3.3V).png|none|thumb|300x300px]]
Usually we deal with femto Farad in VLSI design so you should never be in a situation where you have large capacitors on your chip.

LibrePDK still can generate you a device, you just won't be happy about it.

== Resistors ==
There's two types of resistor structures available: Meander and strip resistors

LibrePDK automatically adds a guard ring around any resistor which should be on a well

'''The meander here is 200 Ohms for GF180A@3.3V'''[[File:LibrePDK Meander Example.png|none|thumb|300x300px]]'''The meander here is 500 Ohms for GF180A@3.3V'''[[File:Strip Resistor Example.png|none|thumb|300x300px]]

== Diodes ==
[[File:Diode Example.png|none|thumb|300x300px|Example of a diode]]
While normal fingered diodes now have been implemented Schottky diodes still are work in progress.

== Schottky diodes ==
Those are not yet implemented

== Transistors ==
In order to make sure that our transistors don't go up in flame, we have to take the hot carrier migration and thermal budget into consideration when we decide what transistor to use and whether it should have only one gate or should be fingered.

LibrePDK takes care of this and chooses the right transistor with the right amount of fingers for you based on the target operating voltage and current you plan to pump through it, you provide.

Additionally, you can also overwrite the thermal budget which usually is assumed to be for an internal circuit which isn't bonded directly to the outside.

When LibrePDK calculates that electron migration and thermal budget constraints don't allow for a single gate transistor it will dynamically create a fingered structure, either with bulk and source connected or not with the proper guard ring.
[[File:Fingered Transistor.png|none|thumb|300x300px|Example of a fingered transistor]]
Libre PDK may also decide to just generate a single gate transistor in cases where there's very little power involved
[[File:Single Gate Example.png|none|thumb|300x300px|Example of a single gate transistor]]

== Pad Cells ==
Last but not least: It contains the [[Pad Cell Generator]] which produces beauties like this
[[File:30mA SG13G2@3V3 v2.png|none|thumb|356x356px]]

LibrePDK

2026-08-15T21:54:42Z

Leviathan: /* Ubuntu */

The LibrePDK is the library driving [[Danube River]] and the [[Pad Cell Generator]]
[[File:LibrePDK.png|none|thumb|695x695px|ALibrePDK screen shot]]
It is responsible for generating discrete parts with specific parameters for a specific process.

The properties of the parts can be optimized by utilizing the calibration values extracted from the measurements of taped out Danube River test wafers.

== Adding a new technology ==
Technologies currently supported can be found in the technologies subfolder.

https://gitlab.libresilicon.com/generator-tools/librepdk/-/tree/master/LibrePDK/technologies?ref_type=heads

New technologies can be added by modifying '''scripts/update_technologies.sh''' and adding a tech.python script to the technologies folder.

After that, LibrePDK should be capable of auto discovering the new process after running the update script.

== Dependencies ==

=== Ubuntu ===
We are using Ubuntu 25.04 in our Docker containers

Simply run<syntaxhighlight lang="bash">apt-get update && apt-get install -y --no-install-recommends \
build-essential cmake git gcc g++ bison flex libfl-dev libeigen3-dev autoconf automake libtool \
libglpk-dev zlib1g-dev libcairo2-dev liblemon-dev libsparsehash-dev pkg-config curl ca-certificates cargo \
rustc sqlite3 bash imagemagick libcairo2-dev tcllib tklib make g++ libreadline-dev libblas-dev \
z3 texlive-latex-recommended unzip glpk-utils libglpk-dev git wget mmv libglu1-mesa-dev libcurl4-gnutls-dev rsync \
pdf2svg libsqlite3-dev git-lfs clang llvm libxaw7-dev time tcl8.6-dev tk8.6-dev tcl software-properties-common vim \
gcc libz-dev ruby ruby-dev libgit2-dev libgit2-glib-1.0-dev curl sudo python3-full python3-dev python3-pip checkinstall \
gosu
</syntaxhighlight>

=== Boost ===
In order for [[LibrePDK#Limbo|Limbo]] to successfully compile we need to install Boost.

We are currently using boost 1.91.0, of which the tar ball can be obtained here https://archives.boost.io/release/1.91.0/source/boost_1_91_0.tar.gz

With the following command Boost can be installed quickly<syntaxhighlight lang="bash">
./bootstrap.sh \
--prefix=/usr \
--with-python-version=3.13

./b2 install
</syntaxhighlight>Note that the Python version we compile boost for is 3.13, because LibrePDK hasn't been tested with any later version.

=== ngspice ===
For the simulation and characterization of standard cells you will need the ngspice frontend and backend library

Currently we are using version 44.2 of ngspice, the tar ball can be obtained from here: https://download.industrysoftware.automation.siemens.com/open-source/ngspice-44.2.tar.gz

==== Backend configuration ====
The backend library is needed for Charlib in order to run characterization of our cells<syntaxhighlight lang="bash">
./autogen.sh
./configure --with-ngshared --enable-xspice --enable-cider --enable-openmp --disable-debug
make -j$(nproc)
make install

</syntaxhighlight>After compilation and installation you should have a libngspice.so in your ldpath which charlib can pick up on and load it.

==== Frontend configuration ====
This will compile and install the ngspice CLI binary which is needed when you wanna simulate your circuits.<syntaxhighlight lang="bash">
./autogen.sh
../configure --with-x --with-readline=yes --enable-xspice
make -j$(nproc)
make install

</syntaxhighlight>ngspice is also used when loading and importing new technologies into LibrePDK

=== OpenVAF models ===
IHP's SG13G2 technology node uses OpenVAF models for the ngspice simulation tool.

The following script will make sure that rust and the OpenVAF tool are present and then
compiles the models into the osdi format and places them into the technology directory
ready to be used by LibrePDK.

Simply run the following script and confirm the installation by checking for the LibrePDK/technologies/spice/SG13G2/devices/*/*.osdi files.

This requires the LibrePDK repo to already have [[LibrePDK#Installation|been cloned and updated]] as shown in.

./scripts/update_ngspice_extensions.sh

=== LP solver ===

Google now officially runs the project and you can get the most recent version from GitHub

Install is by cloning and building it<syntaxhighlight lang="bash">
git clone https://github.com/lp-solve/lp_solve
pushd lp_solve/lpsolve55
rm -rf bin/ux64
sh ccc
popd
</syntaxhighlight> Then you can copy the shared object file in solve/lpsolve55/bin/ux64 into your /usr/lib64 and copy the headers with<syntaxhighlight lang="bash">
mkdir /usr/include/lpsolve
cp lp_solve/*.h /usr/include/lpsolve/
</syntaxhighlight>OR, you can install the system package and devel package with your package manager

=== Lemon ===

That library has been developed by a Hungarian university which doesn't maintain their Mercurial setup. Best approach is to use the version you find in your distribution
=== Limbo ===

The official version of Limbo has been a total mess when it comes to building libs and linking them. I had to make some severe modifications which makes CMake properly build shared object files and detects the system wide installation of the dependencies
using proper CMake detection functions

Just run<syntaxhighlight lang="bash">
git clone https://gitlab.libresilicon.com/leviathan/limbo.git
mkdir Limbo/build
pushd Limbo/build
cmake ..
make
make install
popd
</syntaxhighlight>
== Installation ==
Before you start installing LibrePDK, you first need to [[LibrePDK#Dependencies|install its dependencies]] so that its C++ extensions and other C++ tools compile successfully.

After that, please clone the repo.

pip install [https://gitlab.libresilicon.com/generator-tools/librepdk.git https+git://gitlab.libresilicon.com/generator-tools/librepdk.git]

Don't forget to make sure that all the submodules and their submodules are cloned

git submodule update --init --recursive

For placement of discrete componentes used in more complex components like Driver Circuits, OpAmps, etc. IdeaPlaceExPy is being used.

IdeaPlaceExPy requires the Python system headers to be installed and the virtual env has to match the Python version with which it was compiled.

=== Using LibrePDK in a Virtual Environment (FINAL SETUP) ===
It is recommended to use LibrePDK in a Python virtual environment to avoid dependency conflicts with
system-wide Python packages.

After you've installed all the below dependencies the recommended way of installing the remaining dependencies is to run<syntaxhighlight lang="bash">
uv sync --no-cache
</syntaxhighlight>

== Building your own Docker images ==
Inside of the LibrePDK source folder you will find a script where you can uncomment and comment specific build stages of the multistage Docker build covering all the dependencies

Check out the script '''[https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/scripts/build_docker_images.sh?ref_type=heads scripts/build_docker_images.sh]'''

= Components =
LibrePDK provides generators for the basic components usually found within a VLSI/ULSI design, such as resistors, capacitors, diodes and transistors.

== Capacitors ==
LibrePDK can calculate the specific geometry based on the device rules and available parameters for generating any desired target capacitance value. Below a 50pF capacitor can be seen. You will notice the enormous dimensions of the structure.
[[File:50pF MiMCap (GF180A, 3.3V).png|none|thumb|300x300px]]
Usually we deal with femto Farad in VLSI design so you should never be in a situation where you have large capacitors on your chip.

LibrePDK still can generate you a device, you just won't be happy about it.

== Resistors ==
There's two types of resistor structures available: Meander and strip resistors

LibrePDK automatically adds a guard ring around any resistor which should be on a well

'''The meander here is 200 Ohms for GF180A@3.3V'''[[File:LibrePDK Meander Example.png|none|thumb|300x300px]]'''The meander here is 500 Ohms for GF180A@3.3V'''[[File:Strip Resistor Example.png|none|thumb|300x300px]]

== Diodes ==
[[File:Diode Example.png|none|thumb|300x300px|Example of a diode]]
While normal fingered diodes now have been implemented Schottky diodes still are work in progress.

== Schottky diodes ==
Those are not yet implemented

== Transistors ==
In order to make sure that our transistors don't go up in flame, we have to take the hot carrier migration and thermal budget into consideration when we decide what transistor to use and whether it should have only one gate or should be fingered.

LibrePDK takes care of this and chooses the right transistor with the right amount of fingers for you based on the target operating voltage and current you plan to pump through it, you provide.

Additionally, you can also overwrite the thermal budget which usually is assumed to be for an internal circuit which isn't bonded directly to the outside.

When LibrePDK calculates that electron migration and thermal budget constraints don't allow for a single gate transistor it will dynamically create a fingered structure, either with bulk and source connected or not with the proper guard ring.
[[File:Fingered Transistor.png|none|thumb|300x300px|Example of a fingered transistor]]
Libre PDK may also decide to just generate a single gate transistor in cases where there's very little power involved
[[File:Single Gate Example.png|none|thumb|300x300px|Example of a single gate transistor]]

== Pad Cells ==
Last but not least: It contains the [[Pad Cell Generator]] which produces beauties like this
[[File:30mA SG13G2@3V3 v2.png|none|thumb|356x356px]]

LibrePDK

2026-08-15T21:53:10Z

Leviathan: Undo revision 777 by Leviathan (talk)

The LibrePDK is the library driving [[Danube River]] and the [[Pad Cell Generator]]
[[File:LibrePDK.png|none|thumb|695x695px|ALibrePDK screen shot]]
It is responsible for generating discrete parts with specific parameters for a specific process.

The properties of the parts can be optimized by utilizing the calibration values extracted from the measurements of taped out Danube River test wafers.

== Adding a new technology ==
Technologies currently supported can be found in the technologies subfolder.

https://gitlab.libresilicon.com/generator-tools/librepdk/-/tree/master/LibrePDK/technologies?ref_type=heads

New technologies can be added by modifying '''scripts/update_technologies.sh''' and adding a tech.python script to the technologies folder.

After that, LibrePDK should be capable of auto discovering the new process after running the update script.

== Dependencies ==

=== Ubuntu ===
We are using Ubuntu 25.04 in our Docker containers

Simply run<syntaxhighlight lang="bash">apt install autoconf automake bash bison build-essential ca-certificates cargo checkinstall clang cmake curl flex g++ gcc git git-lfs glpk-utils gosu imagemagick libblas-dev libcairo2-dev libcurl4-gnutls-dev libeigen3-dev libfl-dev libgit2-dev libgit2-glib-1.0-dev libglpk-dev libglu1-mesa-dev liblemon-dev libreadline-dev libsparsehash-dev libsqlite3-dev libtool libxaw7-dev libz-dev llvm make mmv pdf2svg pkg-config python3-dev python3-full python3-pip rsync ruby ruby-dev rustc software-properties-common sqlite3 sudo tcl tcl8.6-dev tcllib texlive-latex-recommended time tk8.6-dev tklib unzip vim wget z3 zlib1g-dev
</syntaxhighlight>

=== Boost ===
In order for [[LibrePDK#Limbo|Limbo]] to successfully compile we need to install Boost.

We are currently using boost 1.91.0, of which the tar ball can be obtained here https://archives.boost.io/release/1.91.0/source/boost_1_91_0.tar.gz

With the following command Boost can be installed quickly<syntaxhighlight lang="bash">
./bootstrap.sh \
--prefix=/usr \
--with-python-version=3.13

./b2 install
</syntaxhighlight>Note that the Python version we compile boost for is 3.13, because LibrePDK hasn't been tested with any later version.

=== ngspice ===
For the simulation and characterization of standard cells you will need the ngspice frontend and backend library

Currently we are using version 44.2 of ngspice, the tar ball can be obtained from here: https://download.industrysoftware.automation.siemens.com/open-source/ngspice-44.2.tar.gz

==== Backend configuration ====
The backend library is needed for Charlib in order to run characterization of our cells<syntaxhighlight lang="bash">
./autogen.sh
./configure --with-ngshared --enable-xspice --enable-cider --enable-openmp --disable-debug
make -j$(nproc)
make install

</syntaxhighlight>After compilation and installation you should have a libngspice.so in your ldpath which charlib can pick up on and load it.

==== Frontend configuration ====
This will compile and install the ngspice CLI binary which is needed when you wanna simulate your circuits.<syntaxhighlight lang="bash">
./autogen.sh
../configure --with-x --with-readline=yes --enable-xspice
make -j$(nproc)
make install

</syntaxhighlight>ngspice is also used when loading and importing new technologies into LibrePDK

=== OpenVAF models ===
IHP's SG13G2 technology node uses OpenVAF models for the ngspice simulation tool.

The following script will make sure that rust and the OpenVAF tool are present and then
compiles the models into the osdi format and places them into the technology directory
ready to be used by LibrePDK.

Simply run the following script and confirm the installation by checking for the LibrePDK/technologies/spice/SG13G2/devices/*/*.osdi files.

This requires the LibrePDK repo to already have [[LibrePDK#Installation|been cloned and updated]] as shown in.

./scripts/update_ngspice_extensions.sh

=== LP solver ===

Google now officially runs the project and you can get the most recent version from GitHub

Install is by cloning and building it<syntaxhighlight lang="bash">
git clone https://github.com/lp-solve/lp_solve
pushd lp_solve/lpsolve55
rm -rf bin/ux64
sh ccc
popd
</syntaxhighlight> Then you can copy the shared object file in solve/lpsolve55/bin/ux64 into your /usr/lib64 and copy the headers with<syntaxhighlight lang="bash">
mkdir /usr/include/lpsolve
cp lp_solve/*.h /usr/include/lpsolve/
</syntaxhighlight>OR, you can install the system package and devel package with your package manager

=== Lemon ===

That library has been developed by a Hungarian university which doesn't maintain their Mercurial setup. Best approach is to use the version you find in your distribution
=== Limbo ===

The official version of Limbo has been a total mess when it comes to building libs and linking them. I had to make some severe modifications which makes CMake properly build shared object files and detects the system wide installation of the dependencies
using proper CMake detection functions

Just run<syntaxhighlight lang="bash">
git clone https://gitlab.libresilicon.com/leviathan/limbo.git
mkdir Limbo/build
pushd Limbo/build
cmake ..
make
make install
popd
</syntaxhighlight>
== Installation ==
Before you start installing LibrePDK, you first need to [[LibrePDK#Dependencies|install its dependencies]] so that its C++ extensions and other C++ tools compile successfully.

After that, please clone the repo.

pip install [https://gitlab.libresilicon.com/generator-tools/librepdk.git https+git://gitlab.libresilicon.com/generator-tools/librepdk.git]

Don't forget to make sure that all the submodules and their submodules are cloned

git submodule update --init --recursive

For placement of discrete componentes used in more complex components like Driver Circuits, OpAmps, etc. IdeaPlaceExPy is being used.

IdeaPlaceExPy requires the Python system headers to be installed and the virtual env has to match the Python version with which it was compiled.

=== Using LibrePDK in a Virtual Environment (FINAL SETUP) ===
It is recommended to use LibrePDK in a Python virtual environment to avoid dependency conflicts with
system-wide Python packages.

After you've installed all the below dependencies the recommended way of installing the remaining dependencies is to run<syntaxhighlight lang="bash">
uv sync --no-cache
</syntaxhighlight>

== Building your own Docker images ==
Inside of the LibrePDK source folder you will find a script where you can uncomment and comment specific build stages of the multistage Docker build covering all the dependencies

Check out the script '''[https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/scripts/build_docker_images.sh?ref_type=heads scripts/build_docker_images.sh]'''

= Components =
LibrePDK provides generators for the basic components usually found within a VLSI/ULSI design, such as resistors, capacitors, diodes and transistors.

== Capacitors ==
LibrePDK can calculate the specific geometry based on the device rules and available parameters for generating any desired target capacitance value. Below a 50pF capacitor can be seen. You will notice the enormous dimensions of the structure.
[[File:50pF MiMCap (GF180A, 3.3V).png|none|thumb|300x300px]]
Usually we deal with femto Farad in VLSI design so you should never be in a situation where you have large capacitors on your chip.

LibrePDK still can generate you a device, you just won't be happy about it.

== Resistors ==
There's two types of resistor structures available: Meander and strip resistors

LibrePDK automatically adds a guard ring around any resistor which should be on a well

'''The meander here is 200 Ohms for GF180A@3.3V'''[[File:LibrePDK Meander Example.png|none|thumb|300x300px]]'''The meander here is 500 Ohms for GF180A@3.3V'''[[File:Strip Resistor Example.png|none|thumb|300x300px]]

== Diodes ==
[[File:Diode Example.png|none|thumb|300x300px|Example of a diode]]
While normal fingered diodes now have been implemented Schottky diodes still are work in progress.

== Schottky diodes ==
Those are not yet implemented

== Transistors ==
In order to make sure that our transistors don't go up in flame, we have to take the hot carrier migration and thermal budget into consideration when we decide what transistor to use and whether it should have only one gate or should be fingered.

LibrePDK takes care of this and chooses the right transistor with the right amount of fingers for you based on the target operating voltage and current you plan to pump through it, you provide.

Additionally, you can also overwrite the thermal budget which usually is assumed to be for an internal circuit which isn't bonded directly to the outside.

When LibrePDK calculates that electron migration and thermal budget constraints don't allow for a single gate transistor it will dynamically create a fingered structure, either with bulk and source connected or not with the proper guard ring.
[[File:Fingered Transistor.png|none|thumb|300x300px|Example of a fingered transistor]]
Libre PDK may also decide to just generate a single gate transistor in cases where there's very little power involved
[[File:Single Gate Example.png|none|thumb|300x300px|Example of a single gate transistor]]

== Pad Cells ==
Last but not least: It contains the [[Pad Cell Generator]] which produces beauties like this
[[File:30mA SG13G2@3V3 v2.png|none|thumb|356x356px]]

LibrePDK

2026-08-15T21:52:41Z

Leviathan: Undo revision 778 by Leviathan (talk)

The LibrePDK is the library driving [[Danube River]] and the [[Pad Cell Generator]]
[[File:LibrePDK.png|none|thumb|695x695px|ALibrePDK screen shot]]
It is responsible for generating discrete parts with specific parameters for a specific process.

The properties of the parts can be optimized by utilizing the calibration values extracted from the measurements of taped out Danube River test wafers.

== Adding a new technology ==
Technologies currently supported can be found in the technologies subfolder.

https://gitlab.libresilicon.com/generator-tools/librepdk/-/tree/master/LibrePDK/technologies?ref_type=heads

New technologies can be added by modifying '''scripts/update_technologies.sh''' and adding a tech.python script to the technologies folder.

After that, LibrePDK should be capable of auto discovering the new process after running the update script.

== Dependencies ==

=== Ubuntu ===
We are using Ubuntu 25.04 in our Docker containers

Simply run<syntaxhighlight lang="bash">apt install autoconf automake bash binutils-dev bison build-essential ca-certificates cargo checkinstall clang cmake curl flex g++ gcc git git-lfs glpk-utils gosu imagemagick libblas-dev libboost-all-dev libboost-python-dev libbz2-dev libcairo2-dev libcurl4-gnutls-dev libeigen3-dev libfl-dev libgit2-dev libgit2-glib-1.0-dev libglpk-dev libglu1-mesa-dev liblemon-dev libreadline-dev libsparsehash-dev libsqlite3-dev libtool libxaw7-dev libxml2-dev libz-dev llvm make mmv pdf2svg pkg-config python-dev python3-dev python3-full python3-pip rapidjson-dev rsync ruby ruby-dev rustc software-properties-common sqlite3 sudo tcl tcl8.6-dev tcllib texlive-latex-recommended time tk8.6-dev tklib unzip vim wget z3 zlib1g-dev
</syntaxhighlight>

=== Boost ===
In order for [[LibrePDK#Limbo|Limbo]] to successfully compile we need to install Boost.

We are currently using boost 1.91.0, of which the tar ball can be obtained here https://archives.boost.io/release/1.91.0/source/boost_1_91_0.tar.gz

With the following command Boost can be installed quickly<syntaxhighlight lang="bash">
./bootstrap.sh \
--prefix=/usr \
--with-python-version=3.13

./b2 install
</syntaxhighlight>Note that the Python version we compile boost for is 3.13, because LibrePDK hasn't been tested with any later version.

=== ngspice ===
For the simulation and characterization of standard cells you will need the ngspice frontend and backend library

Currently we are using version 44.2 of ngspice, the tar ball can be obtained from here: https://download.industrysoftware.automation.siemens.com/open-source/ngspice-44.2.tar.gz

==== Backend configuration ====
The backend library is needed for Charlib in order to run characterization of our cells<syntaxhighlight lang="bash">
./autogen.sh
./configure --with-ngshared --enable-xspice --enable-cider --enable-openmp --disable-debug
make -j$(nproc)
make install

</syntaxhighlight>After compilation and installation you should have a libngspice.so in your ldpath which charlib can pick up on and load it.

==== Frontend configuration ====
This will compile and install the ngspice CLI binary which is needed when you wanna simulate your circuits.<syntaxhighlight lang="bash">
./autogen.sh
../configure --with-x --with-readline=yes --enable-xspice
make -j$(nproc)
make install

</syntaxhighlight>ngspice is also used when loading and importing new technologies into LibrePDK

=== OpenVAF models ===
IHP's SG13G2 technology node uses OpenVAF models for the ngspice simulation tool.

The following script will make sure that rust and the OpenVAF tool are present and then
compiles the models into the osdi format and places them into the technology directory
ready to be used by LibrePDK.

Simply run the following script and confirm the installation by checking for the LibrePDK/technologies/spice/SG13G2/devices/*/*.osdi files.

This requires the LibrePDK repo to already have [[LibrePDK#Installation|been cloned and updated]] as shown in.

./scripts/update_ngspice_extensions.sh

=== LP solver ===

Google now officially runs the project and you can get the most recent version from GitHub

Install is by cloning and building it<syntaxhighlight lang="bash">
git clone https://github.com/lp-solve/lp_solve
pushd lp_solve/lpsolve55
rm -rf bin/ux64
sh ccc
popd
</syntaxhighlight> Then you can copy the shared object file in solve/lpsolve55/bin/ux64 into your /usr/lib64 and copy the headers with<syntaxhighlight lang="bash">
mkdir /usr/include/lpsolve
cp lp_solve/*.h /usr/include/lpsolve/
</syntaxhighlight>OR, you can install the system package and devel package with your package manager

=== Lemon ===

That library has been developed by a Hungarian university which doesn't maintain their Mercurial setup. Best approach is to use the version you find in your distribution
=== Limbo ===

The official version of Limbo has been a total mess when it comes to building libs and linking them. I had to make some severe modifications which makes CMake properly build shared object files and detects the system wide installation of the dependencies
using proper CMake detection functions

Just run<syntaxhighlight lang="bash">
git clone https://gitlab.libresilicon.com/leviathan/limbo.git
mkdir Limbo/build
pushd Limbo/build
cmake ..
make
make install
popd
</syntaxhighlight>
== Installation ==
Before you start installing LibrePDK, you first need to [[LibrePDK#Dependencies|install its dependencies]] so that its C++ extensions and other C++ tools compile successfully.

After that, please clone the repo.

pip install [https://gitlab.libresilicon.com/generator-tools/librepdk.git https+git://gitlab.libresilicon.com/generator-tools/librepdk.git]

Don't forget to make sure that all the submodules and their submodules are cloned

git submodule update --init --recursive

For placement of discrete componentes used in more complex components like Driver Circuits, OpAmps, etc. IdeaPlaceExPy is being used.

IdeaPlaceExPy requires the Python system headers to be installed and the virtual env has to match the Python version with which it was compiled.

=== Using LibrePDK in a Virtual Environment (FINAL SETUP) ===
It is recommended to use LibrePDK in a Python virtual environment to avoid dependency conflicts with
system-wide Python packages.

After you've installed all the below dependencies the recommended way of installing the remaining dependencies is to run<syntaxhighlight lang="bash">
uv sync --no-cache
</syntaxhighlight>

== Building your own Docker images ==
Inside of the LibrePDK source folder you will find a script where you can uncomment and comment specific build stages of the multistage Docker build covering all the dependencies

Check out the script '''[https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/scripts/build_docker_images.sh?ref_type=heads scripts/build_docker_images.sh]'''

= Components =
LibrePDK provides generators for the basic components usually found within a VLSI/ULSI design, such as resistors, capacitors, diodes and transistors.

== Capacitors ==
LibrePDK can calculate the specific geometry based on the device rules and available parameters for generating any desired target capacitance value. Below a 50pF capacitor can be seen. You will notice the enormous dimensions of the structure.
[[File:50pF MiMCap (GF180A, 3.3V).png|none|thumb|300x300px]]
Usually we deal with femto Farad in VLSI design so you should never be in a situation where you have large capacitors on your chip.

LibrePDK still can generate you a device, you just won't be happy about it.

== Resistors ==
There's two types of resistor structures available: Meander and strip resistors

LibrePDK automatically adds a guard ring around any resistor which should be on a well

'''The meander here is 200 Ohms for GF180A@3.3V'''[[File:LibrePDK Meander Example.png|none|thumb|300x300px]]'''The meander here is 500 Ohms for GF180A@3.3V'''[[File:Strip Resistor Example.png|none|thumb|300x300px]]

== Diodes ==
[[File:Diode Example.png|none|thumb|300x300px|Example of a diode]]
While normal fingered diodes now have been implemented Schottky diodes still are work in progress.

== Schottky diodes ==
Those are not yet implemented

== Transistors ==
In order to make sure that our transistors don't go up in flame, we have to take the hot carrier migration and thermal budget into consideration when we decide what transistor to use and whether it should have only one gate or should be fingered.

LibrePDK takes care of this and chooses the right transistor with the right amount of fingers for you based on the target operating voltage and current you plan to pump through it, you provide.

Additionally, you can also overwrite the thermal budget which usually is assumed to be for an internal circuit which isn't bonded directly to the outside.

When LibrePDK calculates that electron migration and thermal budget constraints don't allow for a single gate transistor it will dynamically create a fingered structure, either with bulk and source connected or not with the proper guard ring.
[[File:Fingered Transistor.png|none|thumb|300x300px|Example of a fingered transistor]]
Libre PDK may also decide to just generate a single gate transistor in cases where there's very little power involved
[[File:Single Gate Example.png|none|thumb|300x300px|Example of a single gate transistor]]

== Pad Cells ==
Last but not least: It contains the [[Pad Cell Generator]] which produces beauties like this
[[File:30mA SG13G2@3V3 v2.png|none|thumb|356x356px]]

LibrePDK

2026-08-15T21:51:36Z

Leviathan: /* Ubuntu */

The LibrePDK is the library driving [[Danube River]] and the [[Pad Cell Generator]]
[[File:LibrePDK.png|none|thumb|695x695px|ALibrePDK screen shot]]
It is responsible for generating discrete parts with specific parameters for a specific process.

The properties of the parts can be optimized by utilizing the calibration values extracted from the measurements of taped out Danube River test wafers.

== Adding a new technology ==
Technologies currently supported can be found in the technologies subfolder.

https://gitlab.libresilicon.com/generator-tools/librepdk/-/tree/master/LibrePDK/technologies?ref_type=heads

New technologies can be added by modifying '''scripts/update_technologies.sh''' and adding a tech.python script to the technologies folder.

After that, LibrePDK should be capable of auto discovering the new process after running the update script.

== Dependencies ==

=== Ubuntu ===
We are using Ubuntu 25.04 in our Docker containers

Simply run<syntaxhighlight lang="bash">apt install autoconf automake bash binutils-dev bison build-essential ca-certificates cargo \
checkinstall clang cmake curl flex g++ gcc git git-lfs glpk-utils gosu imagemagick libblas-dev \
libboost-all-dev libboost-python-dev libbz2-dev libcairo2-dev libcurl4-gnutls-dev libeigen3-dev \
libfl-dev libgit2-dev libgit2-glib-1.0-dev libglpk-dev libglu1-mesa-dev liblemon-dev \
libreadline-dev libsparsehash-dev libsqlite3-dev libtool libxaw7-dev libxml2-dev libz-dev \
llvm make mmv pdf2svg pkg-config python-dev python3-dev python3-full python3-pip rapidjson-dev \
rsync ruby ruby-dev rustc software-properties-common sqlite3 sudo tcl tcl8.6-dev tcllib \
texlive-latex-recommended time tk8.6-dev tklib unzip vim wget z3 zlib1g-dev
</syntaxhighlight>

=== Boost ===
In order for [[LibrePDK#Limbo|Limbo]] to successfully compile we need to install Boost.

We are currently using boost 1.91.0, of which the tar ball can be obtained here https://archives.boost.io/release/1.91.0/source/boost_1_91_0.tar.gz

With the following command Boost can be installed quickly<syntaxhighlight lang="bash">
./bootstrap.sh \
--prefix=/usr \
--with-python-version=3.13

./b2 install
</syntaxhighlight>Note that the Python version we compile boost for is 3.13, because LibrePDK hasn't been tested with any later version.

=== ngspice ===
For the simulation and characterization of standard cells you will need the ngspice frontend and backend library

Currently we are using version 44.2 of ngspice, the tar ball can be obtained from here: https://download.industrysoftware.automation.siemens.com/open-source/ngspice-44.2.tar.gz

==== Backend configuration ====
The backend library is needed for Charlib in order to run characterization of our cells<syntaxhighlight lang="bash">
./autogen.sh
./configure --with-ngshared --enable-xspice --enable-cider --enable-openmp --disable-debug
make -j$(nproc)
make install

</syntaxhighlight>After compilation and installation you should have a libngspice.so in your ldpath which charlib can pick up on and load it.

==== Frontend configuration ====
This will compile and install the ngspice CLI binary which is needed when you wanna simulate your circuits.<syntaxhighlight lang="bash">
./autogen.sh
../configure --with-x --with-readline=yes --enable-xspice
make -j$(nproc)
make install

</syntaxhighlight>ngspice is also used when loading and importing new technologies into LibrePDK

=== OpenVAF models ===
IHP's SG13G2 technology node uses OpenVAF models for the ngspice simulation tool.

The following script will make sure that rust and the OpenVAF tool are present and then
compiles the models into the osdi format and places them into the technology directory
ready to be used by LibrePDK.

Simply run the following script and confirm the installation by checking for the LibrePDK/technologies/spice/SG13G2/devices/*/*.osdi files.

This requires the LibrePDK repo to already have [[LibrePDK#Installation|been cloned and updated]] as shown in.

./scripts/update_ngspice_extensions.sh

=== LP solver ===

Google now officially runs the project and you can get the most recent version from GitHub

Install is by cloning and building it<syntaxhighlight lang="bash">
git clone https://github.com/lp-solve/lp_solve
pushd lp_solve/lpsolve55
rm -rf bin/ux64
sh ccc
popd
</syntaxhighlight> Then you can copy the shared object file in solve/lpsolve55/bin/ux64 into your /usr/lib64 and copy the headers with<syntaxhighlight lang="bash">
mkdir /usr/include/lpsolve
cp lp_solve/*.h /usr/include/lpsolve/
</syntaxhighlight>OR, you can install the system package and devel package with your package manager

=== Lemon ===

That library has been developed by a Hungarian university which doesn't maintain their Mercurial setup. Best approach is to use the version you find in your distribution
=== Limbo ===

The official version of Limbo has been a total mess when it comes to building libs and linking them. I had to make some severe modifications which makes CMake properly build shared object files and detects the system wide installation of the dependencies
using proper CMake detection functions

Just run<syntaxhighlight lang="bash">
git clone https://gitlab.libresilicon.com/leviathan/limbo.git
mkdir Limbo/build
pushd Limbo/build
cmake ..
make
make install
popd
</syntaxhighlight>
== Installation ==
Before you start installing LibrePDK, you first need to [[LibrePDK#Dependencies|install its dependencies]] so that its C++ extensions and other C++ tools compile successfully.

After that, please clone the repo.

pip install [https://gitlab.libresilicon.com/generator-tools/librepdk.git https+git://gitlab.libresilicon.com/generator-tools/librepdk.git]

Don't forget to make sure that all the submodules and their submodules are cloned

git submodule update --init --recursive

For placement of discrete componentes used in more complex components like Driver Circuits, OpAmps, etc. IdeaPlaceExPy is being used.

IdeaPlaceExPy requires the Python system headers to be installed and the virtual env has to match the Python version with which it was compiled.

=== Using LibrePDK in a Virtual Environment (FINAL SETUP) ===
It is recommended to use LibrePDK in a Python virtual environment to avoid dependency conflicts with
system-wide Python packages.

After you've installed all the below dependencies the recommended way of installing the remaining dependencies is to run<syntaxhighlight lang="bash">
uv sync --no-cache
</syntaxhighlight>

== Building your own Docker images ==
Inside of the LibrePDK source folder you will find a script where you can uncomment and comment specific build stages of the multistage Docker build covering all the dependencies

Check out the script '''[https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/scripts/build_docker_images.sh?ref_type=heads scripts/build_docker_images.sh]'''

= Components =
LibrePDK provides generators for the basic components usually found within a VLSI/ULSI design, such as resistors, capacitors, diodes and transistors.

== Capacitors ==
LibrePDK can calculate the specific geometry based on the device rules and available parameters for generating any desired target capacitance value. Below a 50pF capacitor can be seen. You will notice the enormous dimensions of the structure.
[[File:50pF MiMCap (GF180A, 3.3V).png|none|thumb|300x300px]]
Usually we deal with femto Farad in VLSI design so you should never be in a situation where you have large capacitors on your chip.

LibrePDK still can generate you a device, you just won't be happy about it.

== Resistors ==
There's two types of resistor structures available: Meander and strip resistors

LibrePDK automatically adds a guard ring around any resistor which should be on a well

'''The meander here is 200 Ohms for GF180A@3.3V'''[[File:LibrePDK Meander Example.png|none|thumb|300x300px]]'''The meander here is 500 Ohms for GF180A@3.3V'''[[File:Strip Resistor Example.png|none|thumb|300x300px]]

== Diodes ==
[[File:Diode Example.png|none|thumb|300x300px|Example of a diode]]
While normal fingered diodes now have been implemented Schottky diodes still are work in progress.

== Schottky diodes ==
Those are not yet implemented

== Transistors ==
In order to make sure that our transistors don't go up in flame, we have to take the hot carrier migration and thermal budget into consideration when we decide what transistor to use and whether it should have only one gate or should be fingered.

LibrePDK takes care of this and chooses the right transistor with the right amount of fingers for you based on the target operating voltage and current you plan to pump through it, you provide.

Additionally, you can also overwrite the thermal budget which usually is assumed to be for an internal circuit which isn't bonded directly to the outside.

When LibrePDK calculates that electron migration and thermal budget constraints don't allow for a single gate transistor it will dynamically create a fingered structure, either with bulk and source connected or not with the proper guard ring.
[[File:Fingered Transistor.png|none|thumb|300x300px|Example of a fingered transistor]]
Libre PDK may also decide to just generate a single gate transistor in cases where there's very little power involved
[[File:Single Gate Example.png|none|thumb|300x300px|Example of a single gate transistor]]

== Pad Cells ==
Last but not least: It contains the [[Pad Cell Generator]] which produces beauties like this
[[File:30mA SG13G2@3V3 v2.png|none|thumb|356x356px]]

LibrePDK

2026-08-15T21:49:23Z

Leviathan: /* Ubuntu */

The LibrePDK is the library driving [[Danube River]] and the [[Pad Cell Generator]]
[[File:LibrePDK.png|none|thumb|695x695px|ALibrePDK screen shot]]
It is responsible for generating discrete parts with specific parameters for a specific process.

The properties of the parts can be optimized by utilizing the calibration values extracted from the measurements of taped out Danube River test wafers.

== Adding a new technology ==
Technologies currently supported can be found in the technologies subfolder.

https://gitlab.libresilicon.com/generator-tools/librepdk/-/tree/master/LibrePDK/technologies?ref_type=heads

New technologies can be added by modifying '''scripts/update_technologies.sh''' and adding a tech.python script to the technologies folder.

After that, LibrePDK should be capable of auto discovering the new process after running the update script.

== Dependencies ==

=== Ubuntu ===
We are using Ubuntu 25.04 in our Docker containers

Simply run<syntaxhighlight lang="bash">apt install autoconf automake bash binutils-dev bison build-essential ca-certificates cargo checkinstall clang cmake curl flex g++ gcc git git-lfs glpk-utils gosu imagemagick libblas-dev libboost-all-dev libboost-python-dev libbz2-dev libcairo2-dev libcurl4-gnutls-dev libeigen3-dev libfl-dev libgit2-dev libgit2-glib-1.0-dev libglpk-dev libglu1-mesa-dev liblemon-dev libreadline-dev libsparsehash-dev libsqlite3-dev libtool libxaw7-dev libxml2-dev libz-dev llvm make mmv pdf2svg pkg-config python-dev python3-dev python3-full python3-pip rapidjson-dev rsync ruby ruby-dev rustc software-properties-common sqlite3 sudo tcl tcl8.6-dev tcllib texlive-latex-recommended time tk8.6-dev tklib unzip vim wget z3 zlib1g-dev
</syntaxhighlight>

=== Boost ===
In order for [[LibrePDK#Limbo|Limbo]] to successfully compile we need to install Boost.

We are currently using boost 1.91.0, of which the tar ball can be obtained here https://archives.boost.io/release/1.91.0/source/boost_1_91_0.tar.gz

With the following command Boost can be installed quickly<syntaxhighlight lang="bash">
./bootstrap.sh \
--prefix=/usr \
--with-python-version=3.13

./b2 install
</syntaxhighlight>Note that the Python version we compile boost for is 3.13, because LibrePDK hasn't been tested with any later version.

=== ngspice ===
For the simulation and characterization of standard cells you will need the ngspice frontend and backend library

Currently we are using version 44.2 of ngspice, the tar ball can be obtained from here: https://download.industrysoftware.automation.siemens.com/open-source/ngspice-44.2.tar.gz

==== Backend configuration ====
The backend library is needed for Charlib in order to run characterization of our cells<syntaxhighlight lang="bash">
./autogen.sh
./configure --with-ngshared --enable-xspice --enable-cider --enable-openmp --disable-debug
make -j$(nproc)
make install

</syntaxhighlight>After compilation and installation you should have a libngspice.so in your ldpath which charlib can pick up on and load it.

==== Frontend configuration ====
This will compile and install the ngspice CLI binary which is needed when you wanna simulate your circuits.<syntaxhighlight lang="bash">
./autogen.sh
../configure --with-x --with-readline=yes --enable-xspice
make -j$(nproc)
make install

</syntaxhighlight>ngspice is also used when loading and importing new technologies into LibrePDK

=== OpenVAF models ===
IHP's SG13G2 technology node uses OpenVAF models for the ngspice simulation tool.

The following script will make sure that rust and the OpenVAF tool are present and then
compiles the models into the osdi format and places them into the technology directory
ready to be used by LibrePDK.

Simply run the following script and confirm the installation by checking for the LibrePDK/technologies/spice/SG13G2/devices/*/*.osdi files.

This requires the LibrePDK repo to already have [[LibrePDK#Installation|been cloned and updated]] as shown in.

./scripts/update_ngspice_extensions.sh

=== LP solver ===

Google now officially runs the project and you can get the most recent version from GitHub

Install is by cloning and building it<syntaxhighlight lang="bash">
git clone https://github.com/lp-solve/lp_solve
pushd lp_solve/lpsolve55
rm -rf bin/ux64
sh ccc
popd
</syntaxhighlight> Then you can copy the shared object file in solve/lpsolve55/bin/ux64 into your /usr/lib64 and copy the headers with<syntaxhighlight lang="bash">
mkdir /usr/include/lpsolve
cp lp_solve/*.h /usr/include/lpsolve/
</syntaxhighlight>OR, you can install the system package and devel package with your package manager

=== Lemon ===

That library has been developed by a Hungarian university which doesn't maintain their Mercurial setup. Best approach is to use the version you find in your distribution
=== Limbo ===

The official version of Limbo has been a total mess when it comes to building libs and linking them. I had to make some severe modifications which makes CMake properly build shared object files and detects the system wide installation of the dependencies
using proper CMake detection functions

Just run<syntaxhighlight lang="bash">
git clone https://gitlab.libresilicon.com/leviathan/limbo.git
mkdir Limbo/build
pushd Limbo/build
cmake ..
make
make install
popd
</syntaxhighlight>
== Installation ==
Before you start installing LibrePDK, you first need to [[LibrePDK#Dependencies|install its dependencies]] so that its C++ extensions and other C++ tools compile successfully.

After that, please clone the repo.

pip install [https://gitlab.libresilicon.com/generator-tools/librepdk.git https+git://gitlab.libresilicon.com/generator-tools/librepdk.git]

Don't forget to make sure that all the submodules and their submodules are cloned

git submodule update --init --recursive

For placement of discrete componentes used in more complex components like Driver Circuits, OpAmps, etc. IdeaPlaceExPy is being used.

IdeaPlaceExPy requires the Python system headers to be installed and the virtual env has to match the Python version with which it was compiled.

=== Using LibrePDK in a Virtual Environment (FINAL SETUP) ===
It is recommended to use LibrePDK in a Python virtual environment to avoid dependency conflicts with
system-wide Python packages.

After you've installed all the below dependencies the recommended way of installing the remaining dependencies is to run<syntaxhighlight lang="bash">
uv sync --no-cache
</syntaxhighlight>

== Building your own Docker images ==
Inside of the LibrePDK source folder you will find a script where you can uncomment and comment specific build stages of the multistage Docker build covering all the dependencies

Check out the script '''[https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/scripts/build_docker_images.sh?ref_type=heads scripts/build_docker_images.sh]'''

= Components =
LibrePDK provides generators for the basic components usually found within a VLSI/ULSI design, such as resistors, capacitors, diodes and transistors.

== Capacitors ==
LibrePDK can calculate the specific geometry based on the device rules and available parameters for generating any desired target capacitance value. Below a 50pF capacitor can be seen. You will notice the enormous dimensions of the structure.
[[File:50pF MiMCap (GF180A, 3.3V).png|none|thumb|300x300px]]
Usually we deal with femto Farad in VLSI design so you should never be in a situation where you have large capacitors on your chip.

LibrePDK still can generate you a device, you just won't be happy about it.

== Resistors ==
There's two types of resistor structures available: Meander and strip resistors

LibrePDK automatically adds a guard ring around any resistor which should be on a well

'''The meander here is 200 Ohms for GF180A@3.3V'''[[File:LibrePDK Meander Example.png|none|thumb|300x300px]]'''The meander here is 500 Ohms for GF180A@3.3V'''[[File:Strip Resistor Example.png|none|thumb|300x300px]]

== Diodes ==
[[File:Diode Example.png|none|thumb|300x300px|Example of a diode]]
While normal fingered diodes now have been implemented Schottky diodes still are work in progress.

== Schottky diodes ==
Those are not yet implemented

== Transistors ==
In order to make sure that our transistors don't go up in flame, we have to take the hot carrier migration and thermal budget into consideration when we decide what transistor to use and whether it should have only one gate or should be fingered.

LibrePDK takes care of this and chooses the right transistor with the right amount of fingers for you based on the target operating voltage and current you plan to pump through it, you provide.

Additionally, you can also overwrite the thermal budget which usually is assumed to be for an internal circuit which isn't bonded directly to the outside.

When LibrePDK calculates that electron migration and thermal budget constraints don't allow for a single gate transistor it will dynamically create a fingered structure, either with bulk and source connected or not with the proper guard ring.
[[File:Fingered Transistor.png|none|thumb|300x300px|Example of a fingered transistor]]
Libre PDK may also decide to just generate a single gate transistor in cases where there's very little power involved
[[File:Single Gate Example.png|none|thumb|300x300px|Example of a single gate transistor]]

== Pad Cells ==
Last but not least: It contains the [[Pad Cell Generator]] which produces beauties like this
[[File:30mA SG13G2@3V3 v2.png|none|thumb|356x356px]]

Pad Frame Generator

2026-08-15T12:20:10Z

Leviathan:

Pad Frame Generator

2026-08-15T12:19:10Z

Leviathan:

[[File:Padframe Example.png|thumb]]
The Pad Frame Generator is part of the [[LibrePDK]] and provides the [[Pad Cell Generator]] functionality.

It's job is to assemble a ready to use pad frame harness, with ESD protection and power rail wire width properly adjusted for accommodating the intended current driving capacity as well as the intended voltage levels to be used.

== Types of Pad Cells produced ==
Currently we support only simple IO [[Pad Cell]], analog cells, and power cells, complex pad cells still are being in development.

The very special impedance compensated pad cell in the works ([[High-Speed Impedance-Compensated Pad Cell]]) is needed in order to hook up DDR4 RAM to our chips or build a PCIe device.

== How to use ==
First pull the docker image for the [[LibrePDK]] in order to make sure the image is up to date by running<syntaxhighlight lang="bash">
docker pull leviathanch/librepdk:latest
</syntaxhighlight>Then you can feed your JSON config for the padframe you have configured to the pad frame generator script contained in the docker image

An example for a paframe config can be found here https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/tests/padframes/padframe_sg13g2_1v2.json?ref_type=heads<syntaxhighlight lang="bash">docker run -it --rm \
-e HOST_UID=$(id -u) -e HOST_GID=$(id -g) \
-v "$(pwd)":/workspace leviathanch/librepdk:latest \
librepdk_padframe_generator -i padframe_config.json \
-o my_padframe</syntaxhighlight>After running the generator you should have a folder named my_padframe containing the LEF, DEF, Magic and all the other files you need for running a full synthesis flow of your designs.

== Installation ==
Since the Pad Frame Generator is part of [[LibrePDK]] you can find the guide on how to install all the dependencies in the [[LibrePDK#Installation|Installation section of the LibrePDK]] page

== Benchmarks ==

=== Initial run ===
<syntaxhighlight lang="bash">
real 20m48.886s
user 20m46.885s
sys 0m3.880s
</syntaxhighlight>

=== Further runs ===
<syntaxhighlight lang="bash">
real 8m43.972s
user 8m40.889s
sys 0m4.139s
</syntaxhighlight>

Pad Frame Generator

2026-08-15T12:18:44Z

Leviathan:

[[File:Padframe Example.png|none|thumb]]
[[File:Pad Frame v2 Example SG13G2@1V2.png|thumb]]
The Pad Frame Generator is part of the [[LibrePDK]] and provides the [[Pad Cell Generator]] functionality.

It's job is to assemble a ready to use pad frame harness, with ESD protection and power rail wire width properly adjusted for accommodating the intended current driving capacity as well as the intended voltage levels to be used.

== Types of Pad Cells produced ==
Currently we support only simple IO [[Pad Cell]], analog cells, and power cells, complex pad cells still are being in development.

The very special impedance compensated pad cell in the works ([[High-Speed Impedance-Compensated Pad Cell]]) is needed in order to hook up DDR4 RAM to our chips or build a PCIe device.

== How to use ==
First pull the docker image for the [[LibrePDK]] in order to make sure the image is up to date by running<syntaxhighlight lang="bash">
docker pull leviathanch/librepdk:latest
</syntaxhighlight>Then you can feed your JSON config for the padframe you have configured to the pad frame generator script contained in the docker image

An example for a paframe config can be found here https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/tests/padframes/padframe_sg13g2_1v2.json?ref_type=heads<syntaxhighlight lang="bash">docker run -it --rm \
-e HOST_UID=$(id -u) -e HOST_GID=$(id -g) \
-v "$(pwd)":/workspace leviathanch/librepdk:latest \
librepdk_padframe_generator -i padframe_config.json \
-o my_padframe</syntaxhighlight>After running the generator you should have a folder named my_padframe containing the LEF, DEF, Magic and all the other files you need for running a full synthesis flow of your designs.

== Installation ==
Since the Pad Frame Generator is part of [[LibrePDK]] you can find the guide on how to install all the dependencies in the [[LibrePDK#Installation|Installation section of the LibrePDK]] page

== Benchmarks ==

=== Initial run ===
<syntaxhighlight lang="bash">
real 20m48.886s
user 20m46.885s
sys 0m3.880s
</syntaxhighlight>

=== Further runs ===
<syntaxhighlight lang="bash">
real 8m43.972s
user 8m40.889s
sys 0m4.139s
</syntaxhighlight>

File:Padframe Example.png

2026-08-15T12:18:31Z

Leviathan:

Screenshot Magic VLSI

Pad Frame Generator

2026-08-13T09:41:38Z

Leviathan: /* Further runs */

[[File:Pad Frame v2 Example SG13G2@1V2.png|thumb]]
The Pad Frame Generator is part of the [[LibrePDK]] and provides the [[Pad Cell Generator]] functionality.

It's job is to assemble a ready to use pad frame harness, with ESD protection and power rail wire width properly adjusted for accommodating the intended current driving capacity as well as the intended voltage levels to be used.

== Types of Pad Cells produced ==
Currently we support only simple IO [[Pad Cell]], analog cells, and power cells, complex pad cells still are being in development.

The very special impedance compensated pad cell in the works ([[High-Speed Impedance-Compensated Pad Cell]]) is needed in order to hook up DDR4 RAM to our chips or build a PCIe device.

== How to use ==
First pull the docker image for the [[LibrePDK]] in order to make sure the image is up to date by running<syntaxhighlight lang="bash">
docker pull leviathanch/librepdk:latest
</syntaxhighlight>Then you can feed your JSON config for the padframe you have configured to the pad frame generator script contained in the docker image

An example for a paframe config can be found here https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/tests/padframes/padframe_sg13g2_1v2.json?ref_type=heads<syntaxhighlight lang="bash">docker run -it --rm \
-e HOST_UID=$(id -u) -e HOST_GID=$(id -g) \
-v "$(pwd)":/workspace leviathanch/librepdk:latest \
librepdk_padframe_generator -i padframe_config.json \
-o my_padframe</syntaxhighlight>After running the generator you should have a folder named my_padframe containing the LEF, DEF, Magic and all the other files you need for running a full synthesis flow of your designs.

== Installation ==
Since the Pad Frame Generator is part of [[LibrePDK]] you can find the guide on how to install all the dependencies in the [[LibrePDK#Installation|Installation section of the LibrePDK]] page

== Benchmarks ==

=== Initial run ===
<syntaxhighlight lang="bash">
real 20m48.886s
user 20m46.885s
sys 0m3.880s
</syntaxhighlight>

=== Further runs ===
<syntaxhighlight lang="bash">
real 8m43.972s
user 8m40.889s
sys 0m4.139s
</syntaxhighlight>

Pad Frame Generator

2026-08-13T09:41:15Z

Leviathan: /* Initial run */

[[File:Pad Frame v2 Example SG13G2@1V2.png|thumb]]
The Pad Frame Generator is part of the [[LibrePDK]] and provides the [[Pad Cell Generator]] functionality.

It's job is to assemble a ready to use pad frame harness, with ESD protection and power rail wire width properly adjusted for accommodating the intended current driving capacity as well as the intended voltage levels to be used.

== Types of Pad Cells produced ==
Currently we support only simple IO [[Pad Cell]], analog cells, and power cells, complex pad cells still are being in development.

The very special impedance compensated pad cell in the works ([[High-Speed Impedance-Compensated Pad Cell]]) is needed in order to hook up DDR4 RAM to our chips or build a PCIe device.

== How to use ==
First pull the docker image for the [[LibrePDK]] in order to make sure the image is up to date by running<syntaxhighlight lang="bash">
docker pull leviathanch/librepdk:latest
</syntaxhighlight>Then you can feed your JSON config for the padframe you have configured to the pad frame generator script contained in the docker image

An example for a paframe config can be found here https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/tests/padframes/padframe_sg13g2_1v2.json?ref_type=heads<syntaxhighlight lang="bash">docker run -it --rm \
-e HOST_UID=$(id -u) -e HOST_GID=$(id -g) \
-v "$(pwd)":/workspace leviathanch/librepdk:latest \
librepdk_padframe_generator -i padframe_config.json \
-o my_padframe</syntaxhighlight>After running the generator you should have a folder named my_padframe containing the LEF, DEF, Magic and all the other files you need for running a full synthesis flow of your designs.

== Installation ==
Since the Pad Frame Generator is part of [[LibrePDK]] you can find the guide on how to install all the dependencies in the [[LibrePDK#Installation|Installation section of the LibrePDK]] page

== Benchmarks ==

=== Initial run ===
<syntaxhighlight lang="bash">
real 20m48.886s
user 20m46.885s
sys 0m3.880s
</syntaxhighlight>

=== Further runs ===
<syntaxhighlight lang="bash">
Successfully generated pad cell elements to: padframe_sg13g2_1v2
Files: io_cell.gds/mag, corner_cell.gds/mag

real 32m18.562s
user 32m9.834s
sys 0m8.844s

</syntaxhighlight>

Pad Frame Generator

2026-08-13T07:02:43Z

Leviathan: /* Benchmarks */

[[File:Pad Frame v2 Example SG13G2@1V2.png|thumb]]
The Pad Frame Generator is part of the [[LibrePDK]] and provides the [[Pad Cell Generator]] functionality.

It's job is to assemble a ready to use pad frame harness, with ESD protection and power rail wire width properly adjusted for accommodating the intended current driving capacity as well as the intended voltage levels to be used.

== Types of Pad Cells produced ==
Currently we support only simple IO [[Pad Cell]], analog cells, and power cells, complex pad cells still are being in development.

The very special impedance compensated pad cell in the works ([[High-Speed Impedance-Compensated Pad Cell]]) is needed in order to hook up DDR4 RAM to our chips or build a PCIe device.

== How to use ==
First pull the docker image for the [[LibrePDK]] in order to make sure the image is up to date by running<syntaxhighlight lang="bash">
docker pull leviathanch/librepdk:latest
</syntaxhighlight>Then you can feed your JSON config for the padframe you have configured to the pad frame generator script contained in the docker image

An example for a paframe config can be found here https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/tests/padframes/padframe_sg13g2_1v2.json?ref_type=heads<syntaxhighlight lang="bash">docker run -it --rm \
-e HOST_UID=$(id -u) -e HOST_GID=$(id -g) \
-v "$(pwd)":/workspace leviathanch/librepdk:latest \
librepdk_padframe_generator -i padframe_config.json \
-o my_padframe</syntaxhighlight>After running the generator you should have a folder named my_padframe containing the LEF, DEF, Magic and all the other files you need for running a full synthesis flow of your designs.

== Installation ==
Since the Pad Frame Generator is part of [[LibrePDK]] you can find the guide on how to install all the dependencies in the [[LibrePDK#Installation|Installation section of the LibrePDK]] page

== Benchmarks ==

=== Initial run ===
<syntaxhighlight lang="bash">
Successfully generated pad cell elements to: padframe_sg13g2_1v2
Files: io_cell.gds/mag, corner_cell.gds/mag

real 36m55.595s
user 36m36.021s
sys 0m6.958s
</syntaxhighlight>

=== Further runs ===
<syntaxhighlight lang="bash">
Successfully generated pad cell elements to: padframe_sg13g2_1v2
Files: io_cell.gds/mag, corner_cell.gds/mag

real 32m18.562s
user 32m9.834s
sys 0m8.844s

</syntaxhighlight>

Pad Frame Generator

2026-08-13T06:23:40Z

Leviathan:

[[File:Pad Frame v2 Example SG13G2@1V2.png|thumb]]
The Pad Frame Generator is part of the [[LibrePDK]] and provides the [[Pad Cell Generator]] functionality.

It's job is to assemble a ready to use pad frame harness, with ESD protection and power rail wire width properly adjusted for accommodating the intended current driving capacity as well as the intended voltage levels to be used.

== Types of Pad Cells produced ==
Currently we support only simple IO [[Pad Cell]], analog cells, and power cells, complex pad cells still are being in development.

The very special impedance compensated pad cell in the works ([[High-Speed Impedance-Compensated Pad Cell]]) is needed in order to hook up DDR4 RAM to our chips or build a PCIe device.

== How to use ==
First pull the docker image for the [[LibrePDK]] in order to make sure the image is up to date by running<syntaxhighlight lang="bash">
docker pull leviathanch/librepdk:latest
</syntaxhighlight>Then you can feed your JSON config for the padframe you have configured to the pad frame generator script contained in the docker image

An example for a paframe config can be found here https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/tests/padframes/padframe_sg13g2_1v2.json?ref_type=heads<syntaxhighlight lang="bash">docker run -it --rm \
-e HOST_UID=$(id -u) -e HOST_GID=$(id -g) \
-v "$(pwd)":/workspace leviathanch/librepdk:latest \
librepdk_padframe_generator -i padframe_config.json \
-o my_padframe</syntaxhighlight>After running the generator you should have a folder named my_padframe containing the LEF, DEF, Magic and all the other files you need for running a full synthesis flow of your designs.

== Installation ==
Since the Pad Frame Generator is part of [[LibrePDK]] you can find the guide on how to install all the dependencies in the [[LibrePDK#Installation|Installation section of the LibrePDK]] page

== Benchmarks ==

=== Initial run ===
<syntaxhighlight lang="bash">
Creating magic wrapper for padframe
Using Magic tech file: /run/media/leviathan/dde9e2a1-4a6e-4d1b-afec-7c557d080ef8/LibrePDK/librepdk/LibrePDK/technologies/magic_tech/SG13G2/libresilicon.tech
Changing back to top directory for padframe

Successfully generated pad cell elements to: padframe_sg13g2_1v2
Files: io_cell.gds/mag, corner_cell.gds/mag

real 36m55.595s
user 36m36.021s
sys 0m6.958s
</syntaxhighlight>