LibreSilicon - User contributions [en]

Danube River

2025-11-24T02:50:42Z

Leviathan: /* Successful tapeouts */

[https://gitlab.libresilicon.com/generator-tools/danube-river Danube River] is a tool, which generates you GDS2 files which you then can manufacture with your prototype process flow in order to validate parameters and adjust your recipes until the values are within a desired range.

== Use cases ==

=== Setting up a new fab ===
In case you wanna build a new factory, you basically tape out your Danube River layout over and over again while adjusting the recipes and design rules until the structures aren't broken anymore under the microscope and the values you measure match the predictions you've calculated.
[[File:Danube For New Foundry.png|none|thumb|600x600px|Danube River flow for setting up a new fab]]

=== Setting up support for an existing fab ===
In case you already have a working process and foundry available, but you're not sure that the timing characteristics they've provided are accurate, you can use Danube River for extracting your own timing characteristics.
[[File:Danube For Existing Foundry.png|none|thumb|600x600px|Danube River flow for supporting existing process]]

== Successful tapeouts ==

So far, the only opportunity we had to try the new test layout generator, was with Global Foundries on their 180nm node, of which the result can be seen in the picture below:
[[File:Danube GF180.png|A successful tapeout with GF180|none|thumb|400x400px|alt=A successful tapeout with GF180]]The tapeout happened with the GDS2 files from the patch level at commit 42f33bb0988a81749da30af46769e721983bb5b1:
https://gitlab.libresilicon.com/generator-tools/danube-river/-/tree/42f33bb0988a81749da30af46769e721983bb5b1

McMaster made a zoomable animated image where you even can zoom in so much that you can read the text

https://siliconpr0n.org/map/efabless/gf180mcu-mpw18h1-18100001/mcmaster_mz_mit20x/#x=8416&y=11120&z=2

== GDS2 view ==
The upper left section in the above image corresponds with the layout extracted from KLayout, when opening up the [https://gitlab.libresilicon.com/generator-tools/danube-river/-/blob/master/tapeout/gf180.gds?ref_type=heads layout used for the tape-out]
[[File:KLayout view- Danube GF180.png|none|thumb|500x500px|KLayout view of the Danube GF180 layout]]

== Structures ==
The Danube test wafer has the purpose of allowing to characterize basic analog properties resulting from the manufacturing process flow.

Each of those properties measured can be linked to a specific recipe in the process flow, which allows to fine tune a process and all its process recipes through repeatedly manufacturing and measuring the Danube river layout.

The Danube river contains 3 types of devices, which allows you to determine edge parameters:

* Resistors
* Capacitors
* Transistors

=== Resistors ===
There's three types of resistive test structures on Danube River, due to variations in sheet resistance vs. area and length requirements.

For each sheet resistance characterization there's each a vertical and horizontal configuration in order to catch any potential variance in sheet resistance due to the orientation, which might occur due to the crystal orientation of the substrate being used, like <100>, <110>, and <111><ref>https://www.universitywafer.com/silicon-orientation.html</ref>

After having determined the voltage over each test resistor, when applying a constant current, the resistance can be calculated using simple Ohm's law <math>R={U \over I}</math>

==== Strip Resistors ====
The most simple form of a resistor simply is a straight sheet resistor between pad 1/2 and 3/4 for the vertical sheet resistance characterization and pad 1/4 to 2/3 for horizontal characterization respectively.[[File:Strip resistors.png|none|thumb|KLayout view of strip resistors]]The resistance is being measured by applying a constant current between two of the pads and measuring the voltage over the other two pads.

Horizontal resistor: Apply constant current over 1 (one) and 2 (two), measure voltage over 4 (four) and 3 (three)

Vertical resistor: Apply constant current over 2 (two) and 3 (three), measure voltage over 1 (one) and 4 (four)

==== Small Meander Resistors ====
Danube River checks during generation whether the initial sheet resistance estimate in the initial calculated value map would result in a straight sheet resistor which still fits between the pads.

If the target resistance of for instance 100 Ohms can not be fit between the pads using a straight resistor, Danube River will generate a Meander structure instead, which if small enough for fitting between the pads will be placed as shown below.[[File:Small Meander Resistors.png|none|thumb|KLayout view of Small Meander Resistors]]The resistance is being measured by applying a constant current between two of the pads and measuring the voltage over the other two pads.

Horizontal resistor: Apply constant current over 2 (two) and 3 (three), measure voltage over 1 (one) and 4 (four)

Vertical resistor: Apply constant current over 1 (one) and 2 (two), measure voltage over 4 (four) and 3 (three)

==== Large Meander Resistors ====
[[File:Large Meander Resistors.png|none|thumb|KLayout view of Large Meander Resistors]]The resistance is being measured by applying a constant current between two of the pads and measuring the voltage over the other two pads.

Horizontal resistor: Apply constant current over 1 (one) and 4 (four), measure voltage over 2 (two) and 3 (three)

Vertical resistor: Apply constant current over 4 (four) and 3 (three), measure voltage over 1 (one) and 2 (two)

=== Capacitors ===
Those capacitors are of interest when it comes to determining parasitic factors like leakage current as well as parasitic capacity between layers.

The values extracted from measuring those structures will go into the optimization functions of the [[StdCellLib]] generator as well as the [[Pad Cell Generator]]

Below some of the capacitors on the test wafer can be seen in more detail.
[[File:Capacitors in GDS2.png|none|frame|Closeup of capacitors in KLayout]]With each capacitor pad 3 (three) and 4 (four) are connected to one electrode, 1 (one) and 2 (two) to the second electrode.

There's several ways of measuring the impedance of those structures,. Devices like keysight can directly measure the capacity and also an impedance vs. frequency curve.

=== Transistors ===
On Danube River there are those very small structures connected the four pads, which for a change aren't connected and configured in a Kelvin configuration, because the pads go to source, drain, gate and bulk each.[[File:Transistor Structures.png|none|thumb|View of Transistor Structures in KLayout]]In the closeup below you can see an annotated zoom in onto one of the structures, with each contact being labeled.
[[File:Closeup FETs.png|none|thumb|Closeup FETs]]
Those structures are probably the most difficult ones to identify.

It's the smallest ones without any pads being shorted to each other with large strips.

Simply use the Field Effect characterization function in your keysight or so and determine the gain and other values.

The pad assignments are:

# ONE: Source
# TWO: Gate
# THREE: Bulk
# FOUR: Drain

== Setup and Generation ==

You can either pull the latest Docker image, build your own Docker image using the Docker file linked below, or go through the Docker file and install the dependencies locally:

https://gitlab.libresilicon.com/leviathan/docker-files/-/blob/master/tools/Dockerfile?ref_type=heads<nowiki/>'

A pre-built Docker image has been pushed to leviathan's Dockerhub, and can be retrieved by running
docker pull leviathanch/libresilicon-tools:latest
In case you are adding a new technology node in [[LibrePDK]], it's better you install everything locally, make a pull request and wait until your technology node is being included in the Docker build

Generating a new test wafer is as easy as providing it the wafer configuration as well as the name of the output GDSII file, it will also generate you a PDF with all the structures and info on how to measure it as well as a CSV file with the coordinates for automated measurement.

Installing the dependencies, minus the LaTeX stuff (see the Docker file for it), basically goes something like
python3 -m venv .venv
. .venv/bin/activate
pip install git+<nowiki>https://gitlab.libresilicon.com/generator-tools/librepdk.git</nowiki>
git clone <nowiki>https://gitlab.libresilicon.com/generator-tools/danube-river.git</nowiki>
cd danube-river && pip install . && cd ..
You can for instance run this command for generating the wafer for LS1U (LibreSilicon 1 micron)
. .venv/bin/activate
cd danube-river
danube_generate -c configs/kacst-ls1u.cfg -o tapeout/kacst-ls1u.gds

== Releases and pipelining ==
Check the pipeline artifacts for the most recent generation outputs from out GitLab CI/CD pipeline and see whether the foundry you wanna target already had a Danube River generated and one in tapeout.

As soon as we get more than just GF180, for which we don't even have all the data, we will start providing pages with tables of all the measurements.

https://gitlab.libresilicon.com/generator-tools/danube-river/-/pipelines/130

== References ==
<references />

LibreSilicon 1µm CMOS Process Flow (HKUST NFF)

2025-11-06T16:21:52Z

Leviathan: Integrated TikZ renderer is broken in newest MediaWiki

File:LS1U flow.png

2025-11-06T16:20:58Z

Leviathan:

TikZ flow of LS1U

2025-09-20T19:34:36Z

Leviathan: /* NAND2 (NAND gate) */

A typical pad cell consists of driver logic, ESD protection and a bonding pad, which essentially just is a "large" metal square, big enough to fit a bonding ball needed to attach the bonding wire or solder it to a PCB (flip chip bonding) or onto another carrier substrate chip (chiplet assembly)
[[File:Padcell.png|none|thumb|302x302px|Pad Cell in Magic editor]]

The schematic of the pad cell can generally be broken down into purely combinatory and active analog design components.[[File:Pad Cell Schematics.png|none|thumb|Pad Cell Schematics]]Where we have the two standard logic cells, and inverter and a NAND2 gate (red), transmission gate with level shifting (yellow), a tri-state driver, with 1, 0 and Z (high impedance).(green) and the transistors for pull up and pull down.

== Driver Logic ==
This part of the pad cell is purely combinatorial, and controls based on its pins on the logic side where it's interfacing to the internal logic, what modes should be configured.

For instance, whether the output is enabled, in which case it would either drive current through its driver circuit or pull down to ground in case pull down mode is being set from the internal logic.

It can also be configured for high impedance input, in case OE is disabled.

Various additional functions can be implemented, like for instance impedance and termination resistor calibration in case it's part of a DRAM or PCIe PHY.

In short, the driver logic configures the actual physical properties of the pad depending on what the internal logic tells it to do:

* Set transistors to either drive from the VCC rail to ground or switch towards ground
* Setting whether the driver should be active at all (Output Enable)
* Provide a state engine or other means for configuring the termination resistance to ground.

=== INV (Inverter) ===

=== NAND2 (NAND gate) ===

[[File:NAND2 Gate.png|none|thumb|A NAND2 gate]]

{| class="wikitable" style="text-align:center"
|-
! colspan="3" |NAND gate truth table
|- bgcolor="#ddeeff"
| colspan="2" |'''Input''' ||'''Output'''
|- bgcolor="#ddeeff"
|A||B||A NAND B
|-
|{{no|0}}||{{no2|0}}||{{yes2|1}}
|-
|{{no2|0}}||{{yes2|1}}||{{yes2|1}}
|-
|{{yes2|1}}||{{no2|0}}||{{yes2|1}}
|-
|{{yes2|1}}||{{yes2|1}}||{{no2|0}}
|}

== Driver circuit ==
Internally, transistors of a logic circuit only can drive a few micro amperes of current and are unable to survive driving a load like an LED.

In order to make a chip do something useful driver circuits need to be implemented which can provide the power needed for actually driving loads like making an LED blink or driving a small DC motor.

This is being done in the driver circuit through [[Fingered Transistors]] which turn the low power logic states at its inputs into a state which is useful to the outside world.

== ESD protection ==
The figure below shows an example of the rail-based protection in which the primary dual diodes (D1 and D2), the secondary dual diodes (D3 and D4), the NMOSFET power supply clamp are employed.

The power clamp provides a current path from the power supply pad to the ground pad during various ESD events.

It's the simplest form of the RC-triggered power supply clamp, where the RC network and the inverter chain are designed such that the NMOSFET (M1) remains off during normal operation and turns on during an ESD event. This NMOSFET should be wide enough to handle the ESD current when it is on during an ESD event.
[[File:Rail-based ESD Protection.png|none|thumb|Concept of rail-based ESD Protection. ESD current is redirected to the VDD power rail and then shunted to GND by a power clamp.]]
An example layout found in one of the opened up PDKs available can be seen below
[[File:ESD layout.png|none|thumb|200x200px|Example ESD layout done in Magic]]Consult the following literature for more information: http://www-tcad.stanford.edu/tcad/pubs/theses/chun.pdf

== Bonding pad ==
A bonding pad, unlike other components on an ASIC, do not scale down with the feature size, because their area is defined by the physical sizes of the physical solder ball and bonding wire, respectively the solder pads for flip chip bonding required.
[[File:Chip packaging.png|none|thumb|A drawing of wire bonding to a classical chip package works]]
Below an example the layout of one of the bonding pads in one of the open PDKs currently available can be seen.[[File:Bonding Pad.png|none|thumb|200x200px|Example bonding pad done in Magic]]The bonding pad usually is 120x120 and 200x200 microns in size, but there's packaging methods which require even larger pads, like for instance when performing flip chip bonding with a cheap substrate manufacturer.

For flip chip bonding typically an additional layer with isolation oxide and tin pads will be added wiring the output pads to a pad array over the passivization oxide.

Pad Cell

2025-09-20T19:33:33Z

Leviathan: /* INV (Inverter) */

A typical pad cell consists of driver logic, ESD protection and a bonding pad, which essentially just is a "large" metal square, big enough to fit a bonding ball needed to attach the bonding wire or solder it to a PCB (flip chip bonding) or onto another carrier substrate chip (chiplet assembly)
[[File:Padcell.png|none|thumb|302x302px|Pad Cell in Magic editor]]

The schematic of the pad cell can generally be broken down into purely combinatory and active analog design components.[[File:Pad Cell Schematics.png|none|thumb|Pad Cell Schematics]]Where we have the two standard logic cells, and inverter and a NAND2 gate (red), transmission gate with level shifting (yellow), a tri-state driver, with 1, 0 and Z (high impedance).(green) and the transistors for pull up and pull down.

== Driver Logic ==
This part of the pad cell is purely combinatorial, and controls based on its pins on the logic side where it's interfacing to the internal logic, what modes should be configured.

For instance, whether the output is enabled, in which case it would either drive current through its driver circuit or pull down to ground in case pull down mode is being set from the internal logic.

It can also be configured for high impedance input, in case OE is disabled.

Various additional functions can be implemented, like for instance impedance and termination resistor calibration in case it's part of a DRAM or PCIe PHY.

In short, the driver logic configures the actual physical properties of the pad depending on what the internal logic tells it to do:

* Set transistors to either drive from the VCC rail to ground or switch towards ground
* Setting whether the driver should be active at all (Output Enable)
* Provide a state engine or other means for configuring the termination resistance to ground.

=== INV (Inverter) ===

=== NAND2 (NAND gate) ===

[[File:NAND2 Gate.png|none|thumb|A NAND2 gate]]

{| class="wikitable" style="text-align:center"
|-
! colspan="3" |NAND gate truth table
|- bgcolor="#ddeeff"
| colspan="2" |'''Input''' ||'''Output'''
|- bgcolor="#ddeeff"
|A||B||A NAND B
|-
|{{no2|0}}||{{no2|0}}||{{yes2|1}}
|-
|{{no2|0}}||{{yes2|1}}||{{yes2|1}}
|-
|{{yes2|1}}||{{no2|0}}||{{yes2|1}}
|-
|{{yes2|1}}||{{yes2|1}}||{{no2|0}}
|}

== Driver circuit ==
Internally, transistors of a logic circuit only can drive a few micro amperes of current and are unable to survive driving a load like an LED.

In order to make a chip do something useful driver circuits need to be implemented which can provide the power needed for actually driving loads like making an LED blink or driving a small DC motor.

This is being done in the driver circuit through [[Fingered Transistors]] which turn the low power logic states at its inputs into a state which is useful to the outside world.

== ESD protection ==
The figure below shows an example of the rail-based protection in which the primary dual diodes (D1 and D2), the secondary dual diodes (D3 and D4), the NMOSFET power supply clamp are employed.

The power clamp provides a current path from the power supply pad to the ground pad during various ESD events.

It's the simplest form of the RC-triggered power supply clamp, where the RC network and the inverter chain are designed such that the NMOSFET (M1) remains off during normal operation and turns on during an ESD event. This NMOSFET should be wide enough to handle the ESD current when it is on during an ESD event.
[[File:Rail-based ESD Protection.png|none|thumb|Concept of rail-based ESD Protection. ESD current is redirected to the VDD power rail and then shunted to GND by a power clamp.]]
An example layout found in one of the opened up PDKs available can be seen below
[[File:ESD layout.png|none|thumb|200x200px|Example ESD layout done in Magic]]Consult the following literature for more information: http://www-tcad.stanford.edu/tcad/pubs/theses/chun.pdf

== Bonding pad ==
A bonding pad, unlike other components on an ASIC, do not scale down with the feature size, because their area is defined by the physical sizes of the physical solder ball and bonding wire, respectively the solder pads for flip chip bonding required.
[[File:Chip packaging.png|none|thumb|A drawing of wire bonding to a classical chip package works]]
Below an example the layout of one of the bonding pads in one of the open PDKs currently available can be seen.[[File:Bonding Pad.png|none|thumb|200x200px|Example bonding pad done in Magic]]The bonding pad usually is 120x120 and 200x200 microns in size, but there's packaging methods which require even larger pads, like for instance when performing flip chip bonding with a cheap substrate manufacturer.

For flip chip bonding typically an additional layer with isolation oxide and tin pads will be added wiring the output pads to a pad array over the passivization oxide.