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LibrePDK Padframe SPICE Verification Report GF180A@3.3V

Leviathan — Tue, 01 Sep 2026 16:40:39 GMT

4. Full Dynamic Loopback

← Older revision		Revision as of 16:40, 1 September 2026
(5 intermediate revisions by the same user not shown)
Line 102:		Line 102:
	=== 2. Digital Output Drive (Write) ===		=== 2. Digital Output Drive (Write) ===
	Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:		Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:
			[[File:Sim 2 signal write GF180A@3.3V.png\|thumb\|center\|700px\|Signal Write: Core OUT driving Bonding Pad (0V to 3.3V)]]
	[[File:~~sim_2_signal_write~~.png\|thumb\|center\|700px\|Signal Write: Core OUT driving Bonding Pad (0V to 3.3V)]]

	=== 3. Digital Input Sensing (Read / Hi-Z) ===		=== 3. Digital Input Sensing (Read / Hi-Z) ===
	External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:		External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:
			[[File:Sim 3 signal read hiz GF180A@3.3V.png\|thumb\|center\|700px\|Signal Read: External Bonding Pad voltage sensed at Core IN]]
	[[File:~~sim_3_signal_read_hiz~~.png\|thumb\|center\|700px\|Signal Read: External Bonding Pad voltage sensed at Core IN]]

	=== 4. Full Dynamic Loopback ===		=== 4. Full Dynamic Loopback ===
	End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):		End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):
			[[File:Sim 4 pad to pad loopback GF180A@3.3V.png\|thumb\|center\|700px\|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]
	[[File:~~sim_4_pad_to_pad_loopback~~.png\|thumb\|center\|700px\|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]

	== Physical Verification & GDS Delivery ==		== Physical Verification & GDS Delivery ==

File:Sim 4 pad to pad loopback GF180A@3.3V.png

Leviathan — Tue, 01 Sep 2026 16:38:30 GMT

Leviathan uploaded File:Sim 4 pad to pad loopback GF180A@3.3V.png

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Sim 4 pad to pad loopback GF180A@3.3V

File:Sim 3 signal read hiz GF180A@3.3V.png

Leviathan — Tue, 01 Sep 2026 16:38:06 GMT

Leviathan uploaded File:Sim 3 signal read hiz GF180A@3.3V.png

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Sim 3 signal read hiz GF180A@3.3V

File:Sim 2 signal write GF180A@3.3V.png

Leviathan — Tue, 01 Sep 2026 16:37:41 GMT

Leviathan uploaded File:Sim 2 signal write GF180A@3.3V.png

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Sim 2 signal write GF180A@3.3V

LibrePDK Padframe SPICE Verification Report GF180A@3.3V

Leviathan — Tue, 01 Sep 2026 16:37:12 GMT

File:Sim 1 esd clamping GF180A@3.3V.png

Leviathan — Tue, 01 Sep 2026 16:36:27 GMT

Leviathan uploaded File:Sim 1 esd clamping GF180A@3.3V.png

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Sim 1 esd clamping GF180A@3.3V

Pad Frame Generator

Leviathan — Tue, 01 Sep 2026 16:35:51 GMT

Test cases

← Older revision		Revision as of 16:35, 1 September 2026
Line 31:		Line 31:

	== Test cases ==		== Test cases ==
			Proper ESD and switching behavior has been verified for all supported technologies in LibrePDK and reports for two of the most important test cases have been put onto our wiki page.

			SG13G2 is important because it's a complex high frequency process with many metal layers plus there is an opportunity for cooperating in a tapeout.

			GF180A only has 3 metal layers which best represents low tech nodes, so it was important to verify that we also can produce working pad frames for such a low metal count process.

	Tests have been performed for the sample pad frame configurations for [https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/tests/padframes/padframe_gf180a_3v3.json?ref_type=heads IHP's SG13G2 at 1.2V] and the [https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/tests/padframes/padframe_gf180a_3v3.json?ref_type=heads GF180A process at 3.3V] (by Global Foundries).		Tests have been performed for the sample pad frame configurations for [https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/tests/padframes/padframe_gf180a_3v3.json?ref_type=heads IHP's SG13G2 at 1.2V] and the [https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/tests/padframes/padframe_gf180a_3v3.json?ref_type=heads GF180A process at 3.3V] (by Global Foundries).

LibrePDK Padframe SPICE Verification Report SG13G2@1.2V

Leviathan — Tue, 01 Sep 2026 16:17:03 GMT

Physical Verification & GDS Delivery

← Older revision		Revision as of 16:17, 1 September 2026
(2 intermediate revisions by the same user not shown)
Line 98:		Line 98:
	=== 1. ESD Clamping Event ===		=== 1. ESD Clamping Event ===
	Transient simulation applying a 2kV / 1.33A peak Human Body Model (HBM) current pulse directly to the bonding pad:		Transient simulation applying a 2kV / 1.33A peak Human Body Model (HBM) current pulse directly to the bonding pad:
	[[File:~~sim_1_esd_clamping~~.png\|thumb\|center\|700px\|ESD Diode and Rail Clamping Response under 1.33A Transient Current Pulse]]		☢
			[[File:Sim 1 esd clamping SG13G2@1.2V.png\|thumb\|center\|700px\|ESD Diode and Rail Clamping Response under 1.33A Transient Current Pulse]]

	=== 2. Digital Output Drive (Write) ===		=== 2. Digital Output Drive (Write) ===
	Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:		Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:
	[[File:~~sim_2_signal_write~~.png\|thumb\|center\|700px\|Signal Write: Core OUT driving Bonding Pad (0V to 1.2V)]]		☢
			[[File:Sim 2 signal write SG13G2@1.2V.png\|thumb\|center\|700px\|Signal Write: Core OUT driving Bonding Pad (0V to 1.2V)]]

	=== 3. Digital Input Sensing (Read / Hi-Z) ===		=== 3. Digital Input Sensing (Read / Hi-Z) ===
	External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:		External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:
	[[File:~~sim_3_signal_read_hiz~~.png\|thumb\|center\|700px\|Signal Read: External Bonding Pad voltage sensed at Core IN]]		[[File:Sim 3 signal read hiz SG13G2@1.2V.png\|thumb\|center\|700px\|Signal Read: External Bonding Pad voltage sensed at Core IN]]

	=== 4. Full Dynamic Loopback ===		=== 4. Full Dynamic Loopback ===
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	* '''SPICE Extracted Netlist:''' <code>padframe.spice</code>		* '''SPICE Extracted Netlist:''' <code>padframe.spice</code>
	* '''Simulation Models:''' <code>model.spice</code> / <code>design_header.ngspice</code>		* '''Simulation Models:''' <code>model.spice</code> / <code>design_header.ngspice</code>

	~~[[index.php?title=Category:LibreSilicon Verification Reports]]~~
	~~[[index.php?title=Category:LibrePDK]]~~
	~~[[index.php?title=Category:SG13G2]]~~

File:Sim 1 esd clamping SG13G2@1.2V.png

Leviathan — Tue, 01 Sep 2026 16:14:53 GMT

Leviathan uploaded File:Sim 1 esd clamping SG13G2@1.2V.png

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Sim 1 esd clamping SG13G2@1.2V

File:Sim 2 signal write SG13G2@1.2V.png

Leviathan — Tue, 01 Sep 2026 16:14:26 GMT

Leviathan uploaded File:Sim 2 signal write SG13G2@1.2V.png

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Sim 2 signal write SG13G2@1.2V

File:Sim 3 signal read hiz SG13G2@1.2V.png

Leviathan — Tue, 01 Sep 2026 16:13:53 GMT

Leviathan uploaded File:Sim 3 signal read hiz SG13G2@1.2V.png

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Sim 3 signal read hiz SG13G2@1.2V

LibrePDK Padframe SPICE Verification Report SG13G2@1.2V

Leviathan — Tue, 01 Sep 2026 16:12:50 GMT

← Older revision		Revision as of 16:12, 1 September 2026
(One intermediate revision by the same user not shown)
Line 110:		Line 110:
	=== 4. Full Dynamic Loopback ===		=== 4. Full Dynamic Loopback ===
	End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):		End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):
	[[File:~~sim_4_pad_to_pad_loopback~~.png\|thumb\|center\|700px\|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]		[[File:Sim 4 pad to pad loopback SG13G2@1.2V.png\|thumb\|center\|700px\|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]

	== Physical Verification & GDS Delivery ==		== Physical Verification & GDS Delivery ==
Line 118:		Line 118:
	* '''Simulation Models:''' <code>model.spice</code> / <code>design_header.ngspice</code>		* '''Simulation Models:''' <code>model.spice</code> / <code>design_header.ngspice</code>

	[[Category:LibreSilicon Verification Reports]]		[[index.php?title=Category:LibreSilicon Verification Reports]]
	[[Category:LibrePDK]]		[[index.php?title=Category:LibrePDK]]
	[[Category:SG13G2]]		[[index.php?title=Category:SG13G2]]

File:Sim 4 pad to pad loopback SG13G2@1.2V.png

Leviathan — Tue, 01 Sep 2026 16:10:08 GMT

Leviathan uploaded File:Sim 4 pad to pad loopback SG13G2@1.2V.png

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Sim 4 pad to pad loopback SG13G2@1.2V

LibrePDK Padframe SPICE Verification Report GF180A@3.3V

Leviathan — Tue, 01 Sep 2026 16:08:57 GMT

Created page with "= LibrePDK Padframe SPICE Verification Report = '''Technology:''' IHP SG13G2 (130nm BiCMOS) '''Operating Voltage:''' 3.3 V '''Verification Date:''' 2026-09-01 16:01:45 UTC '''Extracted Netlist:''' <code>padframe.spice</code> (Magic VLSI Hierarchical Extraction) == Executive Summary == {| class="wikitable" style="text-align:center; width:90%;" ! Test Scenario !! Target Net / Pad !! Measured Values !! Design Specification !! Status |- | style="text-align:left;" |..."

New page

= LibrePDK Padframe SPICE Verification Report =

'''Technology:''' IHP SG13G2 (130nm BiCMOS)
'''Operating Voltage:''' 3.3 V
'''Verification Date:''' 2026-09-01 16:01:45 UTC
'''Extracted Netlist:''' <code>padframe.spice</code> (Magic VLSI Hierarchical Extraction)

== Executive Summary ==
{| class="wikitable" style="text-align:center; width:90%;"
! Test Scenario !! Target Net / Pad !! Measured Values !! Design Specification !! Status
|-
| style="text-align:left;" | '''ESD Clamping Transient''' || PAD_GPIO_0 (ESD Clamps) || Peak Clamped: 4.30 V || < 15.0 V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Output Drive (Write)''' || gpio_out_0 → PAD_GPIO_0 || Low: 2.84 V, High: 0.65 V || Rail-to-rail driver transition || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Input Sensing (Read / Hi-Z)''' || PAD_GPIO_1 → gpio_in_1 || Pad 0V → 0.00 V, Pad 3.3V → 2.87 V || Pad 0V -> Core > 0.8V, Pad 3.3V -> Core < 0.2V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Pad-to-Pad Dynamic Loopback''' || PAD_GPIO_0 → PAD_GPIO_1 || Bus: 1.40V / 1.37V | Rx: 2.85V / -0.01V || Full rail-to-rail dynamic loopback across frame || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|}

== Core Signal & Bonding Pad Interface Mapping ==
The LibrePDK padframe generator exposed unique net names defined in the JSON configuration for seamless Coriolis LEF/DEF digital core integration:

{| class="wikitable" style="width:90%; font-family:monospace;"
! Subcircuit Port Name !! Direction !! Interface Type !! Associated Physical Layer
|-
| '''VDD''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''VSS''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''gpio_in_0''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_0''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_0''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_0''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''gpio_in_1''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_1''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_1''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_1''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_miso_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_miso_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_miso_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MISO''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_cs_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_cs_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_cs_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_CS''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_tx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_tx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_tx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_TX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_rx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_rx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_rx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_RX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_sclk_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_sclk_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_sclk_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_SCLK''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_mosi_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_mosi_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_mosi_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MOSI''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|}

== Transient Simulation Waveforms ==

=== 1. ESD Clamping Event ===
Transient simulation applying a 2kV / 1.33A peak Human Body Model (HBM) current pulse directly to the bonding pad:
[[File:sim_1_esd_clamping.png|thumb|center|700px|ESD Diode and Rail Clamping Response under 1.33A Transient Current Pulse]]

=== 2. Digital Output Drive (Write) ===
Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:
[[File:sim_2_signal_write.png|thumb|center|700px|Signal Write: Core OUT driving Bonding Pad (0V to 3.3V)]]

=== 3. Digital Input Sensing (Read / Hi-Z) ===
External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:
[[File:sim_3_signal_read_hiz.png|thumb|center|700px|Signal Read: External Bonding Pad voltage sensed at Core IN]]

=== 4. Full Dynamic Loopback ===
End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):
[[File:sim_4_pad_to_pad_loopback.png|thumb|center|700px|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]

== Physical Verification & GDS Delivery ==
* '''GDSII Top Level:''' <code>padframe.raw.gds</code> / <code>padframe.gds</code>
* '''Magic Layout:''' <code>padframe.mag</code>
* '''SPICE Extracted Netlist:''' <code>padframe.spice</code>
* '''Simulation Models:''' <code>model.spice</code> / <code>design_header.ngspice</code>

[[Category:LibreSilicon Verification Reports]]
[[Category:LibrePDK]]
[[Category:SG13G2]]

LibrePDK Padframe SPICE Verification Report SG13G2@1.2V

Leviathan — Tue, 01 Sep 2026 16:08:24 GMT

Created page with "= LibrePDK Padframe SPICE Verification Report = '''Technology:''' IHP SG13G2 (130nm BiCMOS) '''Operating Voltage:''' 1.2 V '''Verification Date:''' 2026-09-01 16:47:40 UTC '''Extracted Netlist:''' <code>padframe.spice</code> (Magic VLSI Hierarchical Extraction) == Executive Summary == {| class="wikitable" style="text-align:center; width:90%;" ! Test Scenario !! Target Net / Pad !! Measured Values !! Design Specification !! Status |- | style="text-align:left;" |..."

New page

= LibrePDK Padframe SPICE Verification Report =

'''Technology:''' IHP SG13G2 (130nm BiCMOS)
'''Operating Voltage:''' 1.2 V
'''Verification Date:''' 2026-09-01 16:47:40 UTC
'''Extracted Netlist:''' <code>padframe.spice</code> (Magic VLSI Hierarchical Extraction)

== Executive Summary ==
{| class="wikitable" style="text-align:center; width:90%;"
! Test Scenario !! Target Net / Pad !! Measured Values !! Design Specification !! Status
|-
| style="text-align:left;" | '''ESD Clamping Transient''' || PAD_GPIO_0 (ESD Clamps) || Peak Clamped: 2.75 V || < 15.0 V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Output Drive (Write)''' || gpio_out_0 → PAD_GPIO_0 || Low: 0.00 V, High: 1.15 V || Rail-to-rail driver transition || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Input Sensing (Read / Hi-Z)''' || PAD_GPIO_1 → gpio_in_1 || Pad 0V → 0.00 V, Pad 1.2V → 1.15 V || Pad 0V -> Core > 0.8V, Pad 1.2V -> Core < 0.2V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Pad-to-Pad Dynamic Loopback''' || PAD_GPIO_0 → PAD_GPIO_1 || Bus: 0.12V / 1.20V | Rx: 0.00V / 1.15V || Full rail-to-rail dynamic loopback across frame || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|}

== Core Signal & Bonding Pad Interface Mapping ==
The LibrePDK padframe generator exposed unique net names defined in the JSON configuration for seamless Coriolis LEF/DEF digital core integration:

{| class="wikitable" style="width:90%; font-family:monospace;"
! Subcircuit Port Name !! Direction !! Interface Type !! Associated Physical Layer
|-
| '''VDD''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''VSS''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''gpio_in_0''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_0''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_0''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_0''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''gpio_in_1''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_1''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_1''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_1''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_miso_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_miso_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_miso_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MISO''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_cs_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_cs_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_cs_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_CS''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_tx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_tx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_tx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_TX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_rx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_rx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_rx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_RX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_sclk_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_sclk_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_sclk_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_SCLK''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_mosi_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_mosi_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_mosi_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MOSI''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|}

== Transient Simulation Waveforms ==

=== 1. ESD Clamping Event ===
Transient simulation applying a 2kV / 1.33A peak Human Body Model (HBM) current pulse directly to the bonding pad:
[[File:sim_1_esd_clamping.png|thumb|center|700px|ESD Diode and Rail Clamping Response under 1.33A Transient Current Pulse]]

=== 2. Digital Output Drive (Write) ===
Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:
[[File:sim_2_signal_write.png|thumb|center|700px|Signal Write: Core OUT driving Bonding Pad (0V to 1.2V)]]

=== 3. Digital Input Sensing (Read / Hi-Z) ===
External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:
[[File:sim_3_signal_read_hiz.png|thumb|center|700px|Signal Read: External Bonding Pad voltage sensed at Core IN]]

=== 4. Full Dynamic Loopback ===
End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):
[[File:sim_4_pad_to_pad_loopback.png|thumb|center|700px|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]

== Physical Verification & GDS Delivery ==
* '''GDSII Top Level:''' <code>padframe.raw.gds</code> / <code>padframe.gds</code>
* '''Magic Layout:''' <code>padframe.mag</code>
* '''SPICE Extracted Netlist:''' <code>padframe.spice</code>
* '''Simulation Models:''' <code>model.spice</code> / <code>design_header.ngspice</code>

[[Category:LibreSilicon Verification Reports]]
[[Category:LibrePDK]]
[[Category:SG13G2]]

Pad Frame Generator

Leviathan — Tue, 01 Sep 2026 16:07:08 GMT

← Older revision		Revision as of 16:07, 1 September 2026
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	== How to use ==		== How to use ==
			There are two options on how you can run the Pad Frame Generator on your machine, you can go the easy route and use a docker container or you can [[Pad Frame Generator#Installation\|set up LibrePDK locally]].

			An example for a paframe config can be found here [https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/tests/padframes/padframe_sg13g2_1v2.json?ref_type=heads padframe_sg13g2_1v2.json]

			=== Docker ===
	First pull the docker image for the [[LibrePDK]] in order to make sure the image is up to date by running<syntaxhighlight lang="bash">		First pull the docker image for the [[LibrePDK]] in order to make sure the image is up to date by running<syntaxhighlight lang="bash">
	docker pull leviathanch/librepdk:latest		docker pull leviathanch/librepdk:latest
	</syntaxhighlight>Then you can feed your JSON config for the padframe you have configured to the pad frame generator script contained in the docker image		</syntaxhighlight>Then you can feed your JSON config for the padframe you have configured to the pad frame generator script contained in the docker image.

	~~An example for a paframe config can be found here https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/tests/padframes/padframe_sg13g2_1v2.json?ref_type=heads~~<syntaxhighlight lang="bash">docker run -it --rm \		<syntaxhighlight lang="bash">docker run -it --rm \
	-e HOST_UID=$(id -u) -e HOST_GID=$(id -g) \		-e HOST_UID=$(id -u) -e HOST_GID=$(id -g) \
	-v "$(pwd)":/workspace leviathanch/librepdk:latest \		-v "$(pwd)":/workspace leviathanch/librepdk:latest \
	librepdk_padframe_generator -i padframe_config.json \		librepdk_padframe_generator -i padframe_config.json \
	-o my_padframe</syntaxhighlight>After running the generator you should have a folder named my_padframe containing the LEF, DEF, Magic and all the other files you need for running a full synthesis flow of your designs.		-o my_padframe</syntaxhighlight>After running the generator you should have a folder named my_padframe containing the LEF, DEF, Magic and all the other files you need for running a full synthesis flow of your designs.

			=== Run Locally ===
			After [[Pad Frame Generator#Installation\|seting up LibrePDK locally]] you can generate your pad frame by running<syntaxhighlight lang="bash">uv run \
			librepdk_padframe_generator -i padframe_config.json \
			-o my_padframe</syntaxhighlight>

			== Test cases ==
			Tests have been performed for the sample pad frame configurations for [https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/tests/padframes/padframe_gf180a_3v3.json?ref_type=heads IHP's SG13G2 at 1.2V] and the [https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/tests/padframes/padframe_gf180a_3v3.json?ref_type=heads GF180A process at 3.3V] (by Global Foundries).

			Please look at [[LibrePDK Padframe SPICE Verification Report SG13G2@1.2V]] and [[LibrePDK Padframe SPICE Verification Report GF180A@3.3V]] for the simulation verification results and wave forms.

	== Installation ==		== Installation ==
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	== Benchmarks ==		== Benchmarks ==
			Generating all those individual geometries takes a lot of time, an initial generation run can take up to half an hour due to the complexity and size of a pad frame and its pad cells, which is why we introduced component caching.

	=== Initial run ===		=== Initial run ===
	<syntaxhighlight lang="bash">		The initial run for GF180A takes around 20 minutes, IHP and Skywater with even more layers can take up to 32 minutes<syntaxhighlight lang="bash">
	real 20m48.886s		real 20m48.886s
	user 20m46.885s		user 20m46.885s
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	=== Further runs ===		=== Further runs ===
	<syntaxhighlight lang="bash">		During the second run that generation time is cut in half when assembling the padframe and writing it out.<syntaxhighlight lang="bash">
	real 8m43.972s		real 8m43.972s
	user 8m40.889s		user 8m40.889s
	sys 0m4.139s		sys 0m4.139s
	</syntaxhighlight>		</syntaxhighlight>

LibreSilicon stack

Leviathan — Mon, 31 Aug 2026 08:26:20 GMT

Pad Frames

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	=== Pad Cells ===		=== Pad Cells ===
	The [[Pad Cell Generator]] is part of the [[LibrePDK]] and can be used to created custom sets of pad cells with custom rail voltages and you can even define a set of currents your pad frame is supposed to end up driving.		The [[Pad Cell Generator]] is part of the [[LibrePDK]] and can be used to created custom sets of pad cells with custom rail voltages and you can even define a set of currents your pad frame is supposed to end up driving.
	[[File:~~30mA SG13G2@1V2 v2~~.png\|none\|thumb\|~~419x419px\|30mA pad cell for IHPSG13G2 at 1.2V~~]]		[[File:Sg13g2 1v2 io cell 60mA 1p2V.png\|none\|thumb\|padframe_sg13g2_1v2/io_cell_60mA_1p2V/]]
	The pad cell has such thin wires, because the ultimate wire width has to be determined based on the final current which is supposed to be driven by the overall pad frame the cells are being generated for.		The pad cell has such thin wires, because the ultimate wire width has to be determined based on the final current which is supposed to be driven by the overall pad frame the cells are being generated for.
	=== Pad Frames ===		=== Pad Frames ===
	The [[Pad Frame Generator]] has the job of taking in a JSON with pin assignment for the East, North, South and West bank and then calculate the wire dimensions of the overall padframe based on the projected peak currents as well as to choose the right pad cell type for each assigned pin.		The [[Pad Frame Generator]] has the job of taking in a JSON with pin assignment for the East, North, South and West bank and then calculate the wire dimensions of the overall padframe based on the projected peak currents as well as to choose the right pad cell type for each assigned pin.
	[[File:~~Pad Frame v2~~ Example ~~SG13G2@1V2~~.png\|none\|thumb\|Pad Frame Example SG13G2@1.2V]]		[[File:Padframe Example.png\|none\|thumb\|Pad Frame Example SG13G2@1.2V]]
	The resulting output will be a pad frame in Magic, GDS2, LEF and DEF format, which you can use for placing and routing your internal logic to.		The resulting output will be a pad frame in Magic, GDS2, LEF and DEF format, which you can use for placing and routing your internal logic to.

File:Sg13g2 1v2 io cell 60mA 1p2V.png

Leviathan — Mon, 31 Aug 2026 08:16:43 GMT

Leviathan uploaded File:Sg13g2 1v2 io cell 60mA 1p2V.png

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High-Speed Impedance-Compensated Pad Cell

Leviathan — Wed, 19 Aug 2026 06:53:48 GMT

4.4 Pad Capacitance () and ESD Constraints

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	{\| class="wikitable"		{\| class="wikitable"
	\|+ Output Impedance Selection		\|+ Output Impedance Selection
	! Enabled Legs () !! Effective Driver Impedance !! Application Target		! Enabled Legs !! Effective Driver Impedance !! Application Target
	\|-		\|-
	\| 1 \|\| \|\| High-impedance termination leg / Low-power drive		\| 1 \|\| \|\| High-impedance termination leg / Low-power drive
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	Because silicon fabrication tolerances, operating temperature, and fluctuations alter and by up to , dynamic digital calibration is required:		Because silicon fabrication tolerances, operating temperature, and fluctuations alter and by up to , dynamic digital calibration is required:

	An external precision resistor () is tied to a dedicated '''ZQ Pad'''.		An external precision resistor is tied to a dedicated '''ZQ Pad'''.

	An internal state machine (using an analog comparator and SAR or Up/Down counter) adjusts binary weighted calibration vectors (CAL_PCODE[N:0] and CAL_NCODE[N:0]).		An internal state machine (using an analog comparator and SAR or Up/Down counter) adjusts binary weighted calibration vectors (CAL_PCODE[N:0] and CAL_NCODE[N:0]).
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	'''Requirement:''' The Place & Route engine must enforce symmetric -tree routing for signal paths into LEG_0_PREDRV through LEG_N_PREDRV.		'''Requirement:''' The Place & Route engine must enforce symmetric -tree routing for signal paths into LEG_0_PREDRV through LEG_N_PREDRV.
	=== 4.4 Pad Capacitance () and ESD Constraints ===		=== 4.4 Pad Capacitance and ESD Constraints ===
	Paralleling multiple driver transistors increases total junction capacitance on the output pad pin.		Paralleling multiple driver transistors increases total junction capacitance on the output pad pin.

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	'''Step 2: Poly Resistor Characterization'''		'''Step 2: Poly Resistor Characterization'''

	Extract exact sheet resistance () for poly silicon layer in IHP SG13G2 / LibrePDK to dimension the base leg.		Extract exact sheet resistance for poly silicon layer in IHP SG13G2 / LibrePDK to dimension the base leg.

	'''Step 3: ZQ Calibration State Machine Netlist'''		'''Step 3: ZQ Calibration State Machine Netlist'''

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	=== 1. ESD Clamping Event ===		=== 1. ESD Clamping Event ===
	Transient simulation applying a 2kV / 1.33A peak Human Body Model (HBM) current pulse directly to the bonding pad:		Transient simulation applying a 2kV / 1.33A peak Human Body Model (HBM) current pulse directly to the bonding pad:
	[[File:~~sim_1_esd_clamping~~.png\|thumb\|center\|700px\|ESD Diode and Rail Clamping Response under 1.33A Transient Current Pulse]]		[[File:Sim 1 esd clamping GF180A@3.3V.png\|thumb\|center\|700px\|ESD Diode and Rail Clamping Response under 1.33A Transient Current Pulse]]

	=== 2. Digital Output Drive (Write) ===		=== 2. Digital Output Drive (Write) ===
	Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:		Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:

	[[File:sim_2_signal_write.png\|thumb\|center\|700px\|Signal Write: Core OUT driving Bonding Pad (0V to 3.3V)]]		[[File:sim_2_signal_write.png\|thumb\|center\|700px\|Signal Write: Core OUT driving Bonding Pad (0V to 3.3V)]]

	=== 3. Digital Input Sensing (Read / Hi-Z) ===		=== 3. Digital Input Sensing (Read / Hi-Z) ===
	External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:		External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:

	[[File:sim_3_signal_read_hiz.png\|thumb\|center\|700px\|Signal Read: External Bonding Pad voltage sensed at Core IN]]		[[File:sim_3_signal_read_hiz.png\|thumb\|center\|700px\|Signal Read: External Bonding Pad voltage sensed at Core IN]]

	=== 4. Full Dynamic Loopback ===		=== 4. Full Dynamic Loopback ===
	End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):		End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):

	[[File:sim_4_pad_to_pad_loopback.png\|thumb\|center\|700px\|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]		[[File:sim_4_pad_to_pad_loopback.png\|thumb\|center\|700px\|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]

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	* '''Simulation Models:''' <code>model.spice</code> / <code>design_header.ngspice</code>		* '''Simulation Models:''' <code>model.spice</code> / <code>design_header.ngspice</code>

	[[Category:LibreSilicon Verification Reports]]		[[index.php?title=Category:LibreSilicon Verification Reports]]
	[[Category:LibrePDK]]		[[index.php?title=Category:LibrePDK]]
	[[Category:SG13G2]]		[[index.php?title=Category:SG13G2]]