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Basic Tooling

Leviathan — Sat, 30 May 2026 09:34:02 GMT

Rapid Thermal Processing (RTP)

← Older revision		Revision as of 09:34, 30 May 2026
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	== Heat Treatment ==		== Heat Treatment ==
			Heat treatment is critical for several steps like dopant diffusion, in order to control the depth of wells, as well as for depositing materials in a CVD process, like polysilicon and low temperature oxide (LTO) or for forming silicide/salicide thin films reducing the sheet resistance of polysilicon and junctions.

			=== Rapid Thermal Processing (RTP) ===
			This is used for instance for initiating metallurgical reactions between a deposited titanium thin film and the silicon substrate in order to achieve titanium silicide which reduces the resistance of the polisilicon as I do in step 13 of [[LibreSilicon 1µm CMOS Process Flow (HKUST NFF)\|LS1U]] ([[LibreSilicon 1µm CMOS Process Flow (HKUST NFF)#Step 13: Silicidation]])

			=== Tube Furnace (and CVD) ===

	== Photo Lithography ==		== Photo Lithography ==

	== Etching ==		== Etching ==

ESD Verification

Leviathan — Fri, 29 May 2026 13:37:54 GMT

HBS Reverse

← Older revision		Revision as of 13:37, 29 May 2026
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	== ESD Tests ==		== ESD Tests ==
	The energy which would otherwise go through the internal digital logic takes the alternative path of least resistance, which is the two diodes (we're not generating Schottky diodes yet, see the list of devices in [[LibrePDK]]), which we put as close to the bonding pad as possible.		The energy which would otherwise go through the internal digital logic takes the alternative path of least resistance, which is the two diodes (we're not generating Schottky diodes yet, see the list of devices in [[LibrePDK]]), which we put as close to the bonding pad as possible.

			Here are the [https://gitlab.libresilicon.com/generator-tools/librepdk/-/tree/master/tests/esd?ref_type=heads SPICE decks]

	Here a quick drawing to illustrate the configuration.		Here a quick drawing to illustrate the configuration.
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	=== HBS Forward ===		=== HBS Forward ===
	Simulating forward ESD discharge basically simulates the path drawn below		Simulating forward ESD discharge basically simulates the path drawn below
	[[File:ESD forward IHP SG13G2 1V2.png\|thumb\|277x277px\|none]]		[[File:ESD forward IHP SG13G2 1V2.png\|thumb\|277x277px\|none]]The forward discharge results in a cummulative energy of 100-150 micro Jules.
			[[File:Forward Hbm esd dissipation.png\|none\|thumb]]
			The things won't even get warm

	=== HBS Reverse ===		=== HBS Reverse ===
	For the reverse test, it's backwards...		For the reverse test, it's backwards...
	[[File:ESD backwards IHP SG13G2-@ 1v2.png\|none\|thumb\|341x341px]]		[[File:ESD backwards IHP SG13G2-@ 1v2.png\|none\|thumb\|341x341px]]The same graph results from simulating the reverse ESD, because that's how the diodes have been dimensioned
			[[File:Reverse Hbm esd dissipation.png\|none\|thumb]]
			Not matter which direction, things won't even get warm

	== The IHP SG13G2 case ==		== The IHP SG13G2 case ==

File:Forward Hbm esd dissipation.png

Leviathan — Fri, 29 May 2026 13:34:59 GMT

Leviathan uploaded File:Forward Hbm esd dissipation.png

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Forward Hbm esd dissipation

File:Reverse Hbm esd dissipation.png

Leviathan — Fri, 29 May 2026 13:34:22 GMT

Leviathan uploaded File:Reverse Hbm esd dissipation.png

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Reverse Hbm esd dissipation

ESD Verification

Leviathan — Fri, 29 May 2026 13:33:28 GMT

ESD Tests

@@ Line 23: / Line 23: @@
 Here a quick drawing to illustrate the configuration.
-[[File:PAD-VDD-VSS ESD path.png|none|thumb|200x200px]]
+[[File:PAD-VDD-VSS ESD path.png|none|thumb|200x200px]]Running the detailed tests for IHP with<syntaxhighlight lang="bash">
-Inthe case of IHP SG13G2 @ 1.2V the discharge simulation looks like plotted below.
+./tests/run_single_test.sh SG13G2:1.2 padcell
-Here are some simulation values extracted from ngspice
+</syntaxhighlight>
-* '''Peak PAD voltage:''' 1910.869 V
+=== HBS Forward ===
-* '''Peak current:''' 1.314834 A
+Simulating forward ESD discharge basically simulates the path drawn below
-* '''Peak resistor power:''' 2.593 kW  That's over a 1.5 kΩ sense resistor, the power dissipated over the actual diodes is is only 3.144856 µJ
+[[File:ESD forward IHP SG13G2 1V2.png|thumb|277x277px|none]]
-==== HBM ESD Dissipation ====
+=== HBS Reverse ===
-Assuming a typical ESD discharge of a few nanoseconds the energy absorbed by the chip itself is in the '''micro''' Jules range (3.144856 µJ)
+For the reverse test, it's backwards...
+[[File:ESD backwards IHP SG13G2-@ 1v2.png|none|thumb|341x341px]]
 == The IHP SG13G2 case ==

File:ESD backwards IHP SG13G2-@ 1v2.png

Leviathan — Fri, 29 May 2026 13:32:12 GMT

Leviathan uploaded File:ESD backwards IHP SG13G2-@ 1v2.png

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ESD backwards IHP SG13G2-@ 1v2

File:ESD forward IHP SG13G2 1V2.png

Leviathan — Fri, 29 May 2026 13:28:54 GMT

Leviathan uploaded File:ESD forward IHP SG13G2 1V2.png

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ESD forward IHP SG13G2 1V2

ESD Verification

Leviathan — Fri, 29 May 2026 13:01:45 GMT

ESD path: Bonding Path to VSS ESD and VDD ESD

← Older revision		Revision as of 13:01, 29 May 2026
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	* a 1.5 kΩ series resistor		* a 1.5 kΩ series resistor
	* a switched discharge path		* a switched discharge path
	* a bias on <code>NOT_EN</code> so the driver remains disabled during the pulse

	This is just the driver stage test. The input buffer will be having additional tests		This is just the driver stage test. The input buffer will be having additional tests

	== ESD ~~path: Bonding Path to VSS ESD and VDD ESD~~ ==		== ESD Tests ==
	The energy which would otherwise go through the internal digital logic takes the alternative path of least resistance, which is the two diodes (we're not generating Schottky diodes yet, see the list of devices in [[LibrePDK]]), which we put as close to the bonding pad as possible.		The energy which would otherwise go through the internal digital logic takes the alternative path of least resistance, which is the two diodes (we're not generating Schottky diodes yet, see the list of devices in [[LibrePDK]]), which we put as close to the bonding pad as possible.

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	Only in the beginning there's a huge peak in current 1.314834 A, but since it's only a burst of a few nano seconds the ESD diodes handle it with ease		Only in the beginning there's a huge peak in current 1.314834 A, but since it's only a burst of a few nano seconds the ESD diodes handle it with ease

	~~== ESD path from bonding to internal logic ==~~		== The IHP SG13G2 case ==
	~~The second test is the simulation of whether we have a calculated break through between the external bonding pad and the internal GPIO logic going into the digital core logic (center of the die)~~
	~~[[File:ESD path from outside to internal.png\|none\|thumb]]~~
	As you can see (hopefully) in the drawing I quickly made here in my KolourPaint, we simulate the ESD breakthrough path, which is expected to be negligible due to our backwards calculation, from the outside pad based on the Human Body Model through the pad cell, through the digital logic to ground.

	=== The IHP SG13G2 case ===
	Comparing those two you will notice that the pad with the lower operational voltage needs more area.		Comparing those two you will notice that the pad with the lower operational voltage needs more area.

LibrePDK

Leviathan — Fri, 29 May 2026 11:31:28 GMT

Pad Cells

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	== Pad Cells ==		== Pad Cells ==
	Last but not least: It contains the [[Pad Cell Generator]] which produces beauties like this		Last but not least: It contains the [[Pad Cell Generator]] which produces beauties like this
	[[File:~~Io cell 20mA~~@~~1.2V~~.png\|none\|thumb]]		[[File:30mA SG13G2@3V3 v2.png\|none\|thumb\|356x356px]]

Pad Frame Generator

Leviathan — Fri, 29 May 2026 10:25:43 GMT

← Older revision		Revision as of 10:25, 29 May 2026
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	~~The Pad Frame Generator is part of the [[LibrePDK]]~~[[File:~~Preliminary First~~ Pad Frame ~~generated~~.png\|thumb~~\|First Version~~ of ~~a Padframe of IHP's SG13G2 generated by~~ LibrePDK ~~(Still needs some work)~~]]It's job is to assemble a ready to use pad frame harness, with ESD protection and power rail wire width properly adjusted for accommodating the intended current driving capacity as well as the intended voltage levels to be used.		[[File:Pad Frame v2 Example SG13G2@1V2.png\|thumb]]
			The Pad Frame Generator is part of the [[LibrePDK]]
			It's job is to assemble a ready to use pad frame harness, with ESD protection and power rail wire width properly adjusted for accommodating the intended current driving capacity as well as the intended voltage levels to be used.

ESD Verification

Leviathan — Fri, 29 May 2026 10:20:20 GMT

← Older revision		Revision as of 10:20, 29 May 2026
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	After running<syntaxhighlight lang="bash">		After running<syntaxhighlight lang="bash">
	./tests/test_all_padcells.sh ~~visual~~		./tests/test_all_padcells.sh
	</syntaxhighlight>you end up with a folder called "generated_output"		</syntaxhighlight>you end up with a folder called "generated_output"

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	As you can see (hopefully) in the drawing I quickly made here in my KolourPaint, we simulate the ESD breakthrough path, which is expected to be negligible due to our backwards calculation, from the outside pad based on the Human Body Model through the pad cell, through the digital logic to ground.		As you can see (hopefully) in the drawing I quickly made here in my KolourPaint, we simulate the ESD breakthrough path, which is expected to be negligible due to our backwards calculation, from the outside pad based on the Human Body Model through the pad cell, through the digital logic to ground.

	=== The IHP SG13G2 ~~@ 1.2V~~ case ===		=== The IHP SG13G2 case ===
	Comparing those two you will notice that the pad with the lower operational voltage needs more area.		Comparing those two you will notice that the pad with the lower operational voltage needs more area.

	While at first counter intuitive, this is because we're not dealing with Ohm's law here but with solid state physics, such as hot carriers and the such.		While at first counter intuitive, this is because we're not dealing with Ohm's law here but with solid state physics, such as hot carriers and the such.

	~~The~~ thermal budget ~~also plays~~ a ~~role~~ but ~~not as much as electron migration and~~ so.		It's a balance between electron mobility and thermal budget... took a while to code that. It's really complicated physics, but it's now all done in Python so you won't have to solve those partial differential equations yourself.
	[[File:~~Io cell 20mA~~@1.2V.png~~\|none~~\|thumb\|~~300x300px~~\|~~IHP cell~~ for ~~20mA @~~ 1.2V]]		[[File:30mA SG13G2@1V2 v2.png\|left\|thumb\|419x419px\|'''30mA SG13G2@1V2''' ]]
			[[File:30mA SG13G2@3V3 v2.png\|thumb\|335x335px\|30mA SG13G2@3V3]]
			Lets look at those two pad cells here. One is dimensionsed for 30mA at 1.2V and the other at 3.3V

	=== ~~The~~ IHP ~~SG13G2 @~~ 3.3V ~~case ===~~		One would assume that the 3.3V transistors would be larger.
	~~[[File:Io cell 20mA~~.~~png\|none\|thumb]]~~
			However.

			The width of a channel (length of the gate) is being determined by <math display="inline">L_{gate} = I_{target}/I_{sat}</math> with <math>\left [ I_{sat} \right ] = \frac{mA}{uA} </math>

			That however has to be combined with the thermal budget, which gives a minimum area for the energy to be dissipated on.

			In the case of the 1.2V transistors the saturation current of the channel isn't high enough anyway for violating the minimum area requirement because it doesn't have additional doping like the IHP transistor lifted to 3.3V by additional HV doping.

			This doping improves the conductivity of the channel, so the gates had to be scaled up in order to cover enough space for dissipating the energy they conduct.

File:30mA SG13G2@3V3 v2.png

Leviathan — Fri, 29 May 2026 09:47:22 GMT

Leviathan uploaded File:30mA SG13G2@3V3 v2.png

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30mA SG13G2@3V3 v2

Pad Cell Generator

Leviathan — Fri, 29 May 2026 09:41:07 GMT

How to use

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	[[File:~~Io cell 20mA~~@~~1.2V~~.png\|thumb\|~~20mA Pad Cell for IHP~~'s SG13G2@~~1.2V~~]]		[[File:30mA SG13G2@1V2 v2.png\|thumb\|'''Example 30mA SG13G2@1V2 (version 2)''']]
	The LibreSilicon Pad Cell Generator is an extension of the [[LibrePDK]] which besides the driver logic also dynamically generates the mixed signal parts needed for over current and static discharge protection and providing the currents needed for doing useful things with an actual physical chip, like driving an LED or a small motor.		The LibreSilicon Pad Cell Generator is an extension of the [[LibrePDK]] which besides the driver logic also dynamically generates the mixed signal parts needed for over current and static discharge protection and providing the currents needed for doing useful things with an actual physical chip, like driving an LED or a small motor.

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	Running the following script within the LibrePDK folder, after following the installation instructions...<syntaxhighlight lang="bash">		Running the following script within the LibrePDK folder, after following the installation instructions...<syntaxhighlight lang="bash">
	~~#!/bin/bash~~		uv run librepdk_padframe_generator -i tests/padframes/padframe_sg13g2_1v2.json
	~~TECH=SG13G2~~
	~~VOLTAGE=1.2~~
	~~mkdir -p ihp_pads~~
	~~pushd ihp_pads~~
	uv run ~~librepdk_padcell_generator -t $TECH -v $VOLTAGE~~ -i ~~20,30,40,60~~
	~~popd~~
	</syntaxhighlight>You should end up with a set of pad cells dimensioned for 20mA, 30mA, 40mA and 60mA driver strength, plus a demo assembly which looks somewhat like this (still work in progress)		</syntaxhighlight>You should end up with a set of pad cells dimensioned for 20mA, 30mA, 40mA and 60mA driver strength, plus a demo assembly which looks somewhat like this (still work in progress)
	[[File:~~Preliminary First~~ Pad Frame ~~generated~~.png\|none\|thumb]]		[[File:Pad Frame v2 Example SG13G2@1V2.png\|none\|thumb]]

	== Electrical Discharge Protection ==		== Electrical Discharge Protection ==

LibreSilicon stack

Leviathan — Fri, 29 May 2026 09:37:56 GMT

Pad Cells

← Older revision		Revision as of 09:37, 29 May 2026
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	=== Pad Cells ===		=== Pad Cells ===
	The [[Pad Cell Generator]] is part of the [[LibrePDK]] and can be used to created custom sets of pad cells with custom rail voltages and you can even define a set of currents your pad frame is supposed to end up driving.		The [[Pad Cell Generator]] is part of the [[LibrePDK]] and can be used to created custom sets of pad cells with custom rail voltages and you can even define a set of currents your pad frame is supposed to end up driving.
	[[File:~~Io cell 20mA~~.png\|none\|thumb\|~~20mA~~ pad cell for IHPSG13G2 at 1.2V]]		[[File:30mA SG13G2@1V2 v2.png\|none\|thumb\|419x419px\|30mA pad cell for IHPSG13G2 at 1.2V]]
	The pad cell has such thin wires, because the ultimate wire width has to be determined based on the final current which is supposed to be driven by the overall pad frame the cells are being generated for.		The pad cell has such thin wires, because the ultimate wire width has to be determined based on the final current which is supposed to be driven by the overall pad frame the cells are being generated for.
	=== Pad Frames ===		=== Pad Frames ===

File:30mA SG13G2@1V2 v2.png

Leviathan — Fri, 29 May 2026 09:37:17 GMT

Leviathan uploaded File:30mA SG13G2@1V2 v2.png

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30mA SG13G2@1V2 v2

LibreSilicon stack

Leviathan — Fri, 29 May 2026 09:28:30 GMT

Pad Frames

← Older revision		Revision as of 09:28, 29 May 2026
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	The pad cell has such thin wires, because the ultimate wire width has to be determined based on the final current which is supposed to be driven by the overall pad frame the cells are being generated for.		The pad cell has such thin wires, because the ultimate wire width has to be determined based on the final current which is supposed to be driven by the overall pad frame the cells are being generated for.
	=== Pad Frames ===		=== Pad Frames ===
	The [[Pad Frame Generator]] has the job of taking in a JSON with pin assignment for the East, North, South and West bank and then calculate the wire dimensions of the overall padframe based on the projected peak currents as well as to choose the right pad cell type for each assigned pin.[[File:~~Preliminary First~~ Pad Frame ~~generated~~.png\|thumb\|~~An example of an early result of LibrePDK\|none~~]]		The [[Pad Frame Generator]] has the job of taking in a JSON with pin assignment for the East, North, South and West bank and then calculate the wire dimensions of the overall padframe based on the projected peak currents as well as to choose the right pad cell type for each assigned pin.
			[[File:Pad Frame v2 Example SG13G2@1V2.png\|none\|thumb\|Pad Frame Example SG13G2@1.2V]]
	The resulting output will be a pad frame in Magic, GDS2, LEF and DEF format, which you can use for placing and routing your internal logic to.		The resulting output will be a pad frame in Magic, GDS2, LEF and DEF format, which you can use for placing and routing your internal logic to.

File:Pad Frame v2 Example SG13G2@1V2.png

Leviathan — Fri, 29 May 2026 09:27:55 GMT

Leviathan uploaded File:Pad Frame v2 Example SG13G2@1V2.png

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Pad Frame v2 Example SG13G2@1V2

User:HeatherBarden7

HeatherBarden7 — Fri, 29 May 2026 04:09:13 GMT

User account HeatherBarden7 was created

Pad Frame Generator

Leviathan — Thu, 28 May 2026 16:18:33 GMT

← Older revision		Revision as of 16:18, 28 May 2026
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	[[File:Preliminary First Pad Frame generated.png\|thumb\|First Version of a Padframe of IHP's SG13G2 generated by LibrePDK (Still needs some work)]]		The Pad Frame Generator is part of the [[LibrePDK]][[File:Preliminary First Pad Frame generated.png\|thumb\|First Version of a Padframe of IHP's SG13G2 generated by LibrePDK (Still needs some work)]]It's job is to assemble a ready to use pad frame harness, with ESD protection and power rail wire width properly adjusted for accommodating the intended current driving capacity as well as the intended voltage levels to be used.

Pad Cell Generator

Leviathan — Thu, 28 May 2026 16:17:06 GMT

← Older revision		Revision as of 16:17, 28 May 2026
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	[[File:Io cell 20mA@1.2V.png\|thumb\|~~Io cell~~ 20mA@1.2V]]		[[File:Io cell 20mA@1.2V.png\|thumb\|20mA Pad Cell for IHP's SG13G2@1.2V]]
	The LibreSilicon Pad Cell Generator is an extension of the [[LibrePDK]] which besides the driver logic also dynamically generates the mixed signal parts needed for over current and static discharge protection and providing the currents needed for doing useful things with an actual physical chip, like driving an LED or a small motor.		The LibreSilicon Pad Cell Generator is an extension of the [[LibrePDK]] which besides the driver logic also dynamically generates the mixed signal parts needed for over current and static discharge protection and providing the currents needed for doing useful things with an actual physical chip, like driving an LED or a small motor.

Pad Frame Generator

Leviathan — Thu, 28 May 2026 16:16:33 GMT

Created page with "thumb|First Version of a Padframe of IHP's SG13G2 generated by LibrePDK (Still needs some work)"

New page

[[File:Preliminary First Pad Frame generated.png|thumb|First Version of a Padframe of IHP's SG13G2 generated by LibrePDK (Still needs some work)]]

Pad Cell Generator

Leviathan — Thu, 28 May 2026 16:15:58 GMT

← Older revision		Revision as of 16:15, 28 May 2026
(One intermediate revision by the same user not shown)
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			[[File:Io cell 20mA@1.2V.png\|thumb\|Io cell 20mA@1.2V]]
	The LibreSilicon Pad Cell Generator is an extension of the [[LibrePDK]] which besides the driver logic also dynamically generates the mixed signal parts needed for over current and static discharge protection and providing the currents needed for doing useful things with an actual physical chip, like driving an LED or a small motor.		The LibreSilicon Pad Cell Generator is an extension of the [[LibrePDK]] which besides the driver logic also dynamically generates the mixed signal parts needed for over current and static discharge protection and providing the currents needed for doing useful things with an actual physical chip, like driving an LED or a small motor.
	~~[[File:Preliminary First Pad Frame generated.png\|thumb\|First Version of a Padframe of IHP's SG13G2 generated by LibrePDK (Still needs some work)]]~~
	~~<blockquote></blockquote>~~

	== Existing Groundwork ==		== Existing Groundwork ==

LibreSilicon stack

Leviathan — Thu, 28 May 2026 16:15:04 GMT

Pad Cells

← Older revision		Revision as of 16:15, 28 May 2026
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	=== Pad Cells ===		=== Pad Cells ===
	~~[[File:Preliminary First Pad Frame generated.png\|thumb\|An example of an early result of LibrePDK]]~~
	The [[Pad Cell Generator]] is part of the [[LibrePDK]] and can be used to created custom sets of pad cells with custom rail voltages and you can even define a set of currents your pad frame is supposed to end up driving.		The [[Pad Cell Generator]] is part of the [[LibrePDK]] and can be used to created custom sets of pad cells with custom rail voltages and you can even define a set of currents your pad frame is supposed to end up driving.
			[[File:Io cell 20mA.png\|none\|thumb\|20mA pad cell for IHPSG13G2 at 1.2V]]
			The pad cell has such thin wires, because the ultimate wire width has to be determined based on the final current which is supposed to be driven by the overall pad frame the cells are being generated for.
			=== Pad Frames ===
			The [[Pad Frame Generator]] has the job of taking in a JSON with pin assignment for the East, North, South and West bank and then calculate the wire dimensions of the overall padframe based on the projected peak currents as well as to choose the right pad cell type for each assigned pin.[[File:Preliminary First Pad Frame generated.png\|thumb\|An example of an early result of LibrePDK\|none]]

			The resulting output will be a pad frame in Magic, GDS2, LEF and DEF format, which you can use for placing and routing your internal logic to.

	==Physical manufacturing==		==Physical manufacturing==

Basic Tooling

Leviathan — Thu, 28 May 2026 14:26:15 GMT

Created page with "In order to not have to rely on foundries anymore and to truly democratize semiconductor manufacturing equipment, and eliminating the risk of supply chain attacks by eliminating the supply chain all together, a minimum viable lab setup is needed for making semiconductor structures in your shed. In order to manufacture transistors, you need the capability of performing the below basic physical operations on your sample == Lower Particle Count in the Air == == Heat Trea..."

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In order to not have to rely on foundries anymore and to truly democratize semiconductor manufacturing equipment, and eliminating the risk of supply chain attacks by eliminating the supply chain all together, a minimum viable lab setup is needed for making semiconductor structures in your shed.

In order to manufacture transistors, you need the capability of performing the below basic physical operations on your sample

== Lower Particle Count in the Air ==

== Heat Treatment ==

== Photo Lithography ==

== Etching ==

ESD Verification

Leviathan — Thu, 28 May 2026 01:10:44 GMT

ESD Waveforms

← Older revision		Revision as of 01:10, 28 May 2026
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	Inthe case of IHP SG13G2 @ 1.2V the discharge simulation looks like plotted below.		Inthe case of IHP SG13G2 @ 1.2V the discharge simulation looks like plotted below.

	~~File:Hbm esd dissipation (Diodes) SG13G2@3.3V.pngHbm esd dissipation (Diodes) SG13G2@1.2V~~		Here are some simulation values extracted from ngspice

			* '''Peak PAD voltage:''' 1910.869 V
			* '''Peak current:''' 1.314834 A
			* '''Peak resistor power:''' 2.593 kW That's over a 1.5 kΩ sense resistor, the power dissipated over the actual diodes is is only 3.144856 µJ
			* '''Final dissipated energy:''' 3.144856 µJ

			==== HBM ESD Dissipation ====
			Assuming a typical ESD discharge of a few nanoseconds the energy absorbed by the chip itself is in the '''micro''' Jules range (3.144856 µJ)

	You can see how the voltage on the bonding pad drops while the current and power stays very small		That's nothing
	[[File:Hbm esd waveforms.png\|none\|thumb\|335x335px]]		[[File:HBM ESD dissipation SG13G2@1.2V.png\|none\|thumb]]
	~~Hbm esd dissipation (Diodes) SG13G2@1~~.2V
			==== ESD Waveforms ====
			The current flowing through the pad during an ESD event is only 2100 * 1e-10 at its peak.

			You can see how the voltage on the bonding pad drops while the current and power stays very small[[File:Hbm esd waveforms.png\|none\|thumb\|335x335px]]
			2100*0.1nA = 210nA = 0.2uA ... high ohmic inputs when being turned off are doing high ohmic things.

	Just as dimensionsed, the ESD protection does its job		Just as dimensionsed, the ESD protection does its job

			Only in the beginning there's a huge peak in current 1.314834 A, but since it's only a burst of a few nano seconds the ESD diodes handle it with ease

	== ESD path from bonding to internal logic ==		== ESD path from bonding to internal logic ==
	The second test is the simulation of whether we have a calculated break through between the external bonding pad and the internal GPIO logic going into the digital core logic (center of the die)		The second test is the simulation of whether we have a calculated break through between the external bonding pad and the internal GPIO logic going into the digital core logic (center of the die)
	[[File:ESD path from outside to internal.png\|none\|thumb]]		[[File:ESD path from outside to internal.png\|none\|thumb]]
	As you can see (hopefully) in the drawing I quickly made here in my KolourPaint, we simulate the ESD breakthrough path, which is expected to be ~~neglectable~~ due to our backwards calculation, from the outside pad based on the Human Body Model through the pad cell, through the digital logic to ground.		As you can see (hopefully) in the drawing I quickly made here in my KolourPaint, we simulate the ESD breakthrough path, which is expected to be negligible due to our backwards calculation, from the outside pad based on the Human Body Model through the pad cell, through the digital logic to ground.

	=== The IHP SG13G2 @ 1.2V case ===		=== The IHP SG13G2 @ 1.2V case ===
Line 50:		Line 63:
	[[File:Io cell 20mA@1.2V.png\|none\|thumb\|300x300px\|IHP cell for 20mA @ 1.2V]]		[[File:Io cell 20mA@1.2V.png\|none\|thumb\|300x300px\|IHP cell for 20mA @ 1.2V]]

	===~~= HBM ESD Dissipation =~~===		=== The IHP SG13G2 @ 3.3V case ===
	~~Assuming a typical ESD discharge of a few nanoseconds the energy absorbed by the chip itself is in the micro Jules range~~		[[File:Io cell 20mA.png\|none\|thumb]]

	~~That's nothing~~
	~~==== ESD Waveforms ====~~
	~~The current flowing through the pad during an ESD event is only 2100 * 1e-10 at its peak.~~



	~~2100*0.1nA = 210nA = 0.2uA ... high ohmic inputs when being turned off are doing high ohmic things~~.