MediaWiki API result
This is the HTML representation of the JSON format. HTML is good for debugging, but is unsuitable for application use.
Specify the format parameter to change the output format. To see the non-HTML representation of the JSON format, set format=json.
See the complete documentation, or the API help for more information.
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"title": "Expert Assessment on Bulk Contact Geometry for Multi-Fingered MOSFET P-Cells in LibrePDK",
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"timestamp": "2025-10-12T16:05:58Z",
"comment": "Created page with \" == I. Introduction and Fundamental Role of the Bulk Terminal == The design of robust parameterized cells (P-cells) for integrated circuit development, particularly for wide, multi-fingered Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), hinges critically on controlling parasitic elements. Multi-fingered transistors are a common architectural choice in modern very large scale integration (VLSI) design, used primarily to achieve high current driving capabili...\""
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"title": "Analysis: Single Bulk Contact vs. Bulk Contact Ring for a FET",
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"user": "Leviathan",
"timestamp": "2025-10-12T16:04:03Z",
"comment": "Created page with \"This document analyzes the trade-offs between using a single, small bulk contact versus a continuous bulk contact ring (guard ring) around a Field-Effect Transistor (FET). The choice significantly impacts area, performance, and reliability. === Key Concepts === * '''Bulk (or Body):''' The underlying silicon substrate on which the transistor is built. It must be tied to a stable voltage potential (e.g., VSS for NMOS, VDD for PMOS). * '''Bulk Contact:''' The physical con...\""
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"timestamp": "2025-09-26T14:48:35Z",
"comment": "Automatically uploaded by PGFTikZ extension"
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{
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"title": "LibreSilicon 1\u00b5m CMOS Process Flow (HKUST NFF)",
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"user": "Leviathan",
"timestamp": "2025-09-26T13:21:12Z",
"comment": "Created page with \"This document outlines the 1\u00b5m CMOS manufacturing process designed for the Hong Kong University of Science and Technology (HKUST) Nanoelectronics Fabrication Facility (NFF). It is a '''gate-first''' process utilizing polysilicon for the gate electrode and a shallow trench isolation (STI) approach for device isolation. The process is designed for manufacturing the LibreSilicon standard logic cells and is licensed under the Libre Silicon public license. == General Manuf...\""
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{
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"title": "StdCellLib CellLibraries",
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"user": "PhilippGuehring",
"timestamp": "2025-09-24T22:47:35Z",
"comment": "Created page with \"=== ASYNC === These are asynchronous cells, fresh from the research labs * vanberkel1991.cell * ASYNC1.cell * ASYNC2.cell * ASYNC3.cell * MARTIN1989.cell * sutherland1989.cell === LOFTY === These are cells provided by Dan Ravensloft * LOFTY1.cell * LOFTY2.cell === MATH === These are cells for mathematical functions, e.g. Half-Adder and Full-Adder * HAX1.cell * FAX1.cell === MUXES === These are Multiplexers that were generated with our generator for multiplexers:...\""
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{
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"title": "File:Transmission gate.png",
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"user": "Leviathan",
"timestamp": "2025-09-21T19:12:52Z",
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