ESD Verification - Revision history

Leviathan: /* HBS Reverse */

2026-05-29T13:37:54Z

HBS Reverse

← Older revision		Revision as of 13:37, 29 May 2026
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	== ESD Tests ==		== ESD Tests ==
	The energy which would otherwise go through the internal digital logic takes the alternative path of least resistance, which is the two diodes (we're not generating Schottky diodes yet, see the list of devices in [[LibrePDK]]), which we put as close to the bonding pad as possible.		The energy which would otherwise go through the internal digital logic takes the alternative path of least resistance, which is the two diodes (we're not generating Schottky diodes yet, see the list of devices in [[LibrePDK]]), which we put as close to the bonding pad as possible.

			Here are the [https://gitlab.libresilicon.com/generator-tools/librepdk/-/tree/master/tests/esd?ref_type=heads SPICE decks]

	Here a quick drawing to illustrate the configuration.		Here a quick drawing to illustrate the configuration.
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	=== HBS Forward ===		=== HBS Forward ===
	Simulating forward ESD discharge basically simulates the path drawn below		Simulating forward ESD discharge basically simulates the path drawn below
	[[File:ESD forward IHP SG13G2 1V2.png\|thumb\|277x277px\|none]]		[[File:ESD forward IHP SG13G2 1V2.png\|thumb\|277x277px\|none]]The forward discharge results in a cummulative energy of 100-150 micro Jules.
			[[File:Forward Hbm esd dissipation.png\|none\|thumb]]
			The things won't even get warm

	=== HBS Reverse ===		=== HBS Reverse ===
	For the reverse test, it's backwards...		For the reverse test, it's backwards...
	[[File:ESD backwards IHP SG13G2-@ 1v2.png\|none\|thumb\|341x341px]]		[[File:ESD backwards IHP SG13G2-@ 1v2.png\|none\|thumb\|341x341px]]The same graph results from simulating the reverse ESD, because that's how the diodes have been dimensioned
			[[File:Reverse Hbm esd dissipation.png\|none\|thumb]]
			Not matter which direction, things won't even get warm

	== The IHP SG13G2 case ==		== The IHP SG13G2 case ==

Leviathan: /* ESD Tests */

2026-05-29T13:33:28Z

ESD Tests

@@ Line 23: / Line 23: @@
 Here a quick drawing to illustrate the configuration.
-[[File:PAD-VDD-VSS ESD path.png|none|thumb|200x200px]]
+[[File:PAD-VDD-VSS ESD path.png|none|thumb|200x200px]]Running the detailed tests for IHP with<syntaxhighlight lang="bash">
-Inthe case of IHP SG13G2 @ 1.2V the discharge simulation looks like plotted below.
+./tests/run_single_test.sh SG13G2:1.2 padcell
-Here are some simulation values extracted from ngspice
+</syntaxhighlight>
-* '''Peak PAD voltage:''' 1910.869 V
+=== HBS Forward ===
-* '''Peak current:''' 1.314834 A
+Simulating forward ESD discharge basically simulates the path drawn below
-* '''Peak resistor power:''' 2.593 kW  That's over a 1.5 kΩ sense resistor, the power dissipated over the actual diodes is is only 3.144856 µJ
+[[File:ESD forward IHP SG13G2 1V2.png|thumb|277x277px|none]]
-==== HBM ESD Dissipation ====
+=== HBS Reverse ===
-Assuming a typical ESD discharge of a few nanoseconds the energy absorbed by the chip itself is in the '''micro''' Jules range (3.144856 µJ)
+For the reverse test, it's backwards...
+[[File:ESD backwards IHP SG13G2-@ 1v2.png|none|thumb|341x341px]]
 == The IHP SG13G2 case ==

Leviathan: /* ESD path: Bonding Path to VSS ESD and VDD ESD */

2026-05-29T13:01:45Z

ESD path: Bonding Path to VSS ESD and VDD ESD

← Older revision		Revision as of 13:01, 29 May 2026
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	* a 1.5 kΩ series resistor		* a 1.5 kΩ series resistor
	* a switched discharge path		* a switched discharge path
	* a bias on <code>NOT_EN</code> so the driver remains disabled during the pulse

	This is just the driver stage test. The input buffer will be having additional tests		This is just the driver stage test. The input buffer will be having additional tests

	== ESD ~~path: Bonding Path to VSS ESD and VDD ESD~~ ==		== ESD Tests ==
	The energy which would otherwise go through the internal digital logic takes the alternative path of least resistance, which is the two diodes (we're not generating Schottky diodes yet, see the list of devices in [[LibrePDK]]), which we put as close to the bonding pad as possible.		The energy which would otherwise go through the internal digital logic takes the alternative path of least resistance, which is the two diodes (we're not generating Schottky diodes yet, see the list of devices in [[LibrePDK]]), which we put as close to the bonding pad as possible.

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	Only in the beginning there's a huge peak in current 1.314834 A, but since it's only a burst of a few nano seconds the ESD diodes handle it with ease		Only in the beginning there's a huge peak in current 1.314834 A, but since it's only a burst of a few nano seconds the ESD diodes handle it with ease

	~~== ESD path from bonding to internal logic ==~~		== The IHP SG13G2 case ==
	~~The second test is the simulation of whether we have a calculated break through between the external bonding pad and the internal GPIO logic going into the digital core logic (center of the die)~~
	~~[[File:ESD path from outside to internal.png\|none\|thumb]]~~
	As you can see (hopefully) in the drawing I quickly made here in my KolourPaint, we simulate the ESD breakthrough path, which is expected to be negligible due to our backwards calculation, from the outside pad based on the Human Body Model through the pad cell, through the digital logic to ground.

	=== The IHP SG13G2 case ===
	Comparing those two you will notice that the pad with the lower operational voltage needs more area.		Comparing those two you will notice that the pad with the lower operational voltage needs more area.

Leviathan at 10:20, 29 May 2026

2026-05-29T10:20:20Z

← Older revision		Revision as of 10:20, 29 May 2026
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	After running<syntaxhighlight lang="bash">		After running<syntaxhighlight lang="bash">
	./tests/test_all_padcells.sh ~~visual~~		./tests/test_all_padcells.sh
	</syntaxhighlight>you end up with a folder called "generated_output"		</syntaxhighlight>you end up with a folder called "generated_output"

Leviathan: /* The IHP SG13G2 case */

2026-05-29T09:56:25Z

The IHP SG13G2 case

← Older revision		Revision as of 09:56, 29 May 2026
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	The width of a channel (length of the gate) is being determined by <math display="inline">L_{gate} = I_{target}/I_{sat}</math> with <math>\left [ I_{sat} \right ] = \frac{mA}{uA} </math>		The width of a channel (length of the gate) is being determined by <math display="inline">L_{gate} = I_{target}/I_{sat}</math> with <math>\left [ I_{sat} \right ] = \frac{mA}{uA} </math>

			That however has to be combined with the thermal budget, which gives a minimum area for the energy to be dissipated on.

			In the case of the 1.2V transistors the saturation current of the channel isn't high enough anyway for violating the minimum area requirement because it doesn't have additional doping like the IHP transistor lifted to 3.3V by additional HV doping.

			This doping improves the conductivity of the channel, so the gates had to be scaled up in order to cover enough space for dissipating the energy they conduct.

Leviathan: /* The IHP SG13G2 case */

2026-05-29T09:53:35Z

The IHP SG13G2 case

← Older revision		Revision as of 09:53, 29 May 2026
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	However.		However.

	The width of a channel (length of the gate) is being determined by <math display="inline">L_{gate} = I_{target}/I_{sat}</math>		The width of a channel (length of the gate) is being determined by <math display="inline">L_{gate} = I_{target}/I_{sat}</math> with <math>\left [ I_{sat} \right ] = \frac{mA}{uA} </math>

Leviathan: /* The IHP SG13G2 case */

2026-05-29T09:51:47Z

The IHP SG13G2 case

← Older revision		Revision as of 09:51, 29 May 2026
Line 69:		Line 69:
	However.		However.

	The width of a channel (length of the gate) is being determined by <math>L_{gate} = I_{target}/I_{sat}</math>		The width of a channel (length of the gate) is being determined by <math display="inline">L_{gate} = I_{target}/I_{sat}</math>

Leviathan: /* The IHP SG13G2 @ 1.2V case */

2026-05-29T09:51:15Z

The IHP SG13G2 @ 1.2V case

← Older revision		Revision as of 09:51, 29 May 2026
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	As you can see (hopefully) in the drawing I quickly made here in my KolourPaint, we simulate the ESD breakthrough path, which is expected to be negligible due to our backwards calculation, from the outside pad based on the Human Body Model through the pad cell, through the digital logic to ground.		As you can see (hopefully) in the drawing I quickly made here in my KolourPaint, we simulate the ESD breakthrough path, which is expected to be negligible due to our backwards calculation, from the outside pad based on the Human Body Model through the pad cell, through the digital logic to ground.

	=== The IHP SG13G2 ~~@ 1.2V~~ case ===		=== The IHP SG13G2 case ===
	Comparing those two you will notice that the pad with the lower operational voltage needs more area.		Comparing those two you will notice that the pad with the lower operational voltage needs more area.

	While at first counter intuitive, this is because we're not dealing with Ohm's law here but with solid state physics, such as hot carriers and the such.		While at first counter intuitive, this is because we're not dealing with Ohm's law here but with solid state physics, such as hot carriers and the such.

	~~The~~ thermal budget ~~also plays~~ a ~~role~~ but ~~not as much as electron migration and~~ so.		It's a balance between electron mobility and thermal budget... took a while to code that. It's really complicated physics, but it's now all done in Python so you won't have to solve those partial differential equations yourself.
	[[File:~~Io cell 20mA~~@1.2V.png~~\|none~~\|thumb\|~~300x300px~~\|~~IHP cell~~ for ~~20mA @~~ 1.2V]]		[[File:30mA SG13G2@1V2 v2.png\|left\|thumb\|419x419px\|'''30mA SG13G2@1V2''' ]]
			[[File:30mA SG13G2@3V3 v2.png\|thumb\|335x335px\|30mA SG13G2@3V3]]
			Lets look at those two pad cells here. One is dimensionsed for 30mA at 1.2V and the other at 3.3V

	~~=== The IHP SG13G2 @~~ 3.3V ~~case ===~~		One would assume that the 3.3V transistors would be larger.
	~~[[File:Io cell 20mA~~.~~png\|none\|thumb]]~~
			However.

			The width of a channel (length of the gate) is being determined by <math>L_{gate} = I_{target}/I_{sat}</math>

Leviathan: /* ESD Waveforms */

2026-05-28T01:10:44Z

ESD Waveforms

← Older revision		Revision as of 01:10, 28 May 2026
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	Just as dimensionsed, the ESD protection does its job		Just as dimensionsed, the ESD protection does its job

	Only in the beginning there's a huge peak		Only in the beginning there's a huge peak in current 1.314834 A, but since it's only a burst of a few nano seconds the ESD diodes handle it with ease

	== ESD path from bonding to internal logic ==		== ESD path from bonding to internal logic ==

Leviathan: /* ESD path: Bonding Path to VSS ESD and VDD ESD */

2026-05-28T01:09:18Z

ESD path: Bonding Path to VSS ESD and VDD ESD

← Older revision		Revision as of 01:09, 28 May 2026
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	* '''Peak PAD voltage:''' 1910.869 V		* '''Peak PAD voltage:''' 1910.869 V
	* '''Peak current:''' 1.314834 A		* '''Peak current:''' 1.314834 A
	* '''Peak resistor power:''' 2.593 kW That's over a 1.~~5kOhm~~ sense resistor, the power dissipated over the actual diodes is is only 3.144856 µJ		* '''Peak resistor power:''' 2.593 kW That's over a 1.5 kΩ sense resistor, the power dissipated over the actual diodes is is only 3.144856 µJ
	* '''Final dissipated energy:''' 3.144856 µJ		* '''Final dissipated energy:''' 3.144856 µJ