High-Speed Impedance-Compensated Pad Cell - Revision history

Leviathan: /* 4.4 Pad Capacitance () and ESD Constraints */

2026-08-19T06:53:48Z

4.4 Pad Capacitance () and ESD Constraints

← Older revision		Revision as of 06:53, 19 August 2026
Line 31:		Line 31:
	{\| class="wikitable"		{\| class="wikitable"
	\|+ Output Impedance Selection		\|+ Output Impedance Selection
	! Enabled Legs () !! Effective Driver Impedance !! Application Target		! Enabled Legs !! Effective Driver Impedance !! Application Target
	\|-		\|-
	\| 1 \|\| \|\| High-impedance termination leg / Low-power drive		\| 1 \|\| \|\| High-impedance termination leg / Low-power drive
Line 48:		Line 48:
	Because silicon fabrication tolerances, operating temperature, and fluctuations alter and by up to , dynamic digital calibration is required:		Because silicon fabrication tolerances, operating temperature, and fluctuations alter and by up to , dynamic digital calibration is required:

	An external precision resistor () is tied to a dedicated '''ZQ Pad'''.		An external precision resistor is tied to a dedicated '''ZQ Pad'''.

	An internal state machine (using an analog comparator and SAR or Up/Down counter) adjusts binary weighted calibration vectors (CAL_PCODE[N:0] and CAL_NCODE[N:0]).		An internal state machine (using an analog comparator and SAR or Up/Down counter) adjusts binary weighted calibration vectors (CAL_PCODE[N:0] and CAL_NCODE[N:0]).
Line 162:		Line 162:

	'''Requirement:''' The Place & Route engine must enforce symmetric -tree routing for signal paths into LEG_0_PREDRV through LEG_N_PREDRV.		'''Requirement:''' The Place & Route engine must enforce symmetric -tree routing for signal paths into LEG_0_PREDRV through LEG_N_PREDRV.
	=== 4.4 Pad Capacitance () and ESD Constraints ===		=== 4.4 Pad Capacitance and ESD Constraints ===
	Paralleling multiple driver transistors increases total junction capacitance on the output pad pin.		Paralleling multiple driver transistors increases total junction capacitance on the output pad pin.

Line 175:		Line 175:
	'''Step 2: Poly Resistor Characterization'''		'''Step 2: Poly Resistor Characterization'''

	Extract exact sheet resistance () for poly silicon layer in IHP SG13G2 / LibrePDK to dimension the base leg.		Extract exact sheet resistance for poly silicon layer in IHP SG13G2 / LibrePDK to dimension the base leg.

	'''Step 3: ZQ Calibration State Machine Netlist'''		'''Step 3: ZQ Calibration State Machine Netlist'''

Leviathan: /* Predriver Slice Logic Specification */

2026-08-10T22:43:44Z

Predriver Slice Logic Specification

← Older revision		Revision as of 22:43, 10 August 2026
Line 140:		Line 140:
	\| 1 \|\| 1 \|\| 1 \|\| 1 \|\| 1 \|\| 0 \|\| 0		\| 1 \|\| 1 \|\| 1 \|\| 1 \|\| 1 \|\| 0 \|\| 0
	\|}		\|}


	==== Mode Functional Descriptions ====		==== Mode Functional Descriptions ====
	* '''Disabled / Uncalibrated:''' When calibration code bits are low, the slice is fully isolated from the output pad, preventing uncalibrated drive strength contributions.		* '''Disabled / Uncalibrated:''' When calibration code bits are low, the slice is fully isolated from the output pad, preventing uncalibrated drive strength contributions.

Leviathan: /* Predriver Slice Logic Specification */

2026-08-10T22:43:18Z

Predriver Slice Logic Specification

@@ Line 69: / Line 69: @@
 The pre-driver slice controls individual driver leg segments. It evaluates calibration bits (<tt>BIT_CAL_P</tt>, <tt>BIT_CAL_N</tt>), global tri-state enable (<tt>GLOBAL_EN</tt>), and On-Die Termination override (<tt>ODT_EN</tt>) to drive the gates of the output stage (<tt>GATE_P</tt> and <tt>GATE_N</tt>).
-{| class="wikitable" style="text-align:center;"
+{| class="wikitable"
-|+ Predriver Slice Control Truth Table
+|+ Logic Table for predriver_slice
 |-
-! BIT_CAL_P !! BIT_CAL_N !! GLOBAL_EN !! ODT_EN !! DATA_IN !! GATE_P <br/>(Active Low) !! GATE_N <br/>(Active High) !! Operating Mode / Output State
+! colspan="5" | Inputs !! colspan="2" | Outputs
 |-
-| 0 || 0 || X || X || X || 1 (OFF) || 0 (OFF) || '''Leg Disabled / Uncalibrated (Hi-Z)'''
+! DATA_IN !! GLOBAL_EN !! ODT_EN !! BIT_CAL_P !! BIT_CAL_N !! GATE_P !! GATE_N
 |-
-| 1 || 1 || 0 || 0 || X || 1 (OFF) || 0 (OFF) || '''Global Tri-State / Standby (Hi-Z)'''
+| 0 || 0 || 0 || 0 || 0 || Z || Z
 |-
-| 1 || 1 || 1 || 0 || 1 || 0 (ON) || 0 (OFF) || '''Active Drive HIGH (Pull-Up)'''
+| 0 || 0 || 0 || 0 || 1 || Z || Z
 |-
-| 1 || 1 || 1 || 0 || 0 || 1 (OFF) || 1 (ON) || '''Active Drive LOW (Pull-Down)'''
+| 0 || 0 || 0 || 1 || 0 || 0 || 0
 |-
-| 1 || 1 || X || 1 || X || 0 (ON) || 1 (ON) || '''On-Die Termination (ODT Active)'''
+| 0 || 0 || 0 || 1 || 1 || 0 || 0
 |-
-| 1 || 0 || 1 || 0 || 1 || 0 (ON) || 0 (OFF) || '''Asymmetric Sourcing (Pull-Up Only)'''
+| 0 || 0 || 1 || 0 || 0 || Z || Z
 |-
-| 0 || 1 || 1 || 0 || 0 || 1 (OFF) || 1 (ON) || '''Asymmetric Sinking (Pull-Down Only)'''
+| 0 || 0 || 1 || 0 || 1 || 1 || 0
 |}
 ==== Mode Functional Descriptions ====

Leviathan at 21:48, 10 August 2026

2026-08-10T21:48:08Z

← Older revision		Revision as of 21:48, 10 August 2026
Line 66:		Line 66:
	[[File:Predriver slice schematic.png\|none\|thumb\|800x800px\|Preslice Schematic]]		[[File:Predriver slice schematic.png\|none\|thumb\|800x800px\|Preslice Schematic]]

	== Predriver Slice Logic Specification ==		=== Predriver Slice Logic Specification ===

	The pre-driver slice controls individual driver leg segments. It evaluates calibration bits (<tt>BIT_CAL_P</tt>, <tt>BIT_CAL_N</tt>), global tri-state enable (<tt>GLOBAL_EN</tt>), and On-Die Termination override (<tt>ODT_EN</tt>) to drive the gates of the output stage (<tt>GATE_P</tt> and <tt>GATE_N</tt>).		The pre-driver slice controls individual driver leg segments. It evaluates calibration bits (<tt>BIT_CAL_P</tt>, <tt>BIT_CAL_N</tt>), global tri-state enable (<tt>GLOBAL_EN</tt>), and On-Die Termination override (<tt>ODT_EN</tt>) to drive the gates of the output stage (<tt>GATE_P</tt> and <tt>GATE_N</tt>).

Line 90:		Line 89:
	\|}		\|}

	=== Mode Functional Descriptions ===		==== Mode Functional Descriptions ====
	* '''Disabled / Uncalibrated:''' When calibration code bits are low, the slice is fully isolated from the output pad, preventing uncalibrated drive strength contributions.		* '''Disabled / Uncalibrated:''' When calibration code bits are low, the slice is fully isolated from the output pad, preventing uncalibrated drive strength contributions.
	* '''Active Drive:''' Normal push-pull switching mode when <tt>GLOBAL_EN</tt> is asserted and <tt>ODT_EN</tt> is deasserted.		* '''Active Drive:''' Normal push-pull switching mode when <tt>GLOBAL_EN</tt> is asserted and <tt>ODT_EN</tt> is deasserted.

Leviathan: /* Segmented Driver Logic */

2026-08-10T21:47:14Z

Segmented Driver Logic

@@ Line 60: / Line 60: @@
 === Segmented Driver Logic ===
-<syntaxhighlight lang="json">
+The JSON netlist for the segmented driver logic can be found here: https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/designs/driver_logic_segmented.json?ref_type=heads
 === Pre-Drive Slice ===

Leviathan at 21:45, 10 August 2026

2026-08-10T21:45:58Z

@@ Line 181: / Line 181: @@
 The JSON netlist for the preslice can be found here: https://gitlab.libresilicon.com/generator-tools/librepdk/-/blob/master/designs/predriver_slice.json?ref_type=heads
 [[File:Predriver slice schematic.png|none|thumb|800x800px|Preslice Schematic]]
 == 4. LibrePDK Physical Layout & Silicon Process Rules ==

Leviathan: /* Pre-Drive Slice */

2026-08-10T21:41:17Z

Pre-Drive Slice

Show changes

Leviathan at 18:06, 10 August 2026

2026-08-10T18:06:34Z

Show changes

Leviathan: /* 2.1 Multi-Leg / Segmented Output Driver */

2026-08-10T18:04:57Z

2.1 Multi-Leg / Segmented Output Driver

← Older revision		Revision as of 18:04, 10 August 2026
Line 23:		Line 23:
	Rather than a single monolithic transistor, the output driver array is divided into parallel driver legs (typically to ).		Rather than a single monolithic transistor, the output driver array is divided into parallel driver legs (typically to ).

	Each leg consists of a pull-up PMOS and pull-down NMOS in series with a precision poly-silicon resistor ().		Each leg consists of a pull-up PMOS and pull-down NMOS in series with a precision poly-silicon resistor.

	Leg parameters are sized such that the total leg resistance satisfies:		Leg parameters are sized such that the total leg resistance satisfies:
Line 30:		Line 30:

	{\| class="wikitable"		{\| class="wikitable"
	\|+ Output Impedance Selection ()		\|+ Output Impedance Selection
	! Enabled Legs () !! Effective Driver Impedance () !! Application Target		! Enabled Legs () !! Effective Driver Impedance !! Application Target
	\|-		\|-
	\| 1 \|\| \|\| High-impedance termination leg / Low-power drive		\| 1 \|\| \|\| High-impedance termination leg / Low-power drive

Leviathan: /* 3. Pre-Driver & Driver Netlist Topology (JSON) */

2026-08-10T12:15:15Z

3. Pre-Driver & Driver Netlist Topology (JSON)

← Older revision		Revision as of 12:15, 10 August 2026
Line 55:		Line 55:

	== 3. Pre-Driver & Driver Netlist Topology (JSON) ==		== 3. Pre-Driver & Driver Netlist Topology (JSON) ==
	To support automated Place & Route (PnR) inside LibreSilicon, the single-channel gate output format must be refactored into a segmented pre-driver slice array (driver_logic_segmented).<syntaxhighlight lang="json">		To support automated Place & Route (PnR) inside LibreSilicon, the single-channel gate output format must be refactored into a segmented pre-driver slice array (driver_logic_segmented).

			This is just a draft, we still have to re-introduce complex sub-components in [[LibrePDK]]<syntaxhighlight lang="json">
	{		{
	"name": "driver_logic_segmented",		"name": "driver_logic_segmented",