LibrePDK Padframe SPICE Verification Report GF180A@3.3V - Revision history

Leviathan: /* 4. Full Dynamic Loopback */

2026-09-01T16:40:39Z

4. Full Dynamic Loopback

← Older revision		Revision as of 16:40, 1 September 2026
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	=== 4. Full Dynamic Loopback ===		=== 4. Full Dynamic Loopback ===
	End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):		End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):
	[[~~File:~~File:Sim 4 pad to pad loopback GF180A@3.3V.png\|thumb\|center\|700px\|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]		[[File:Sim 4 pad to pad loopback GF180A@3.3V.png\|thumb\|center\|700px\|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]

	== Physical Verification & GDS Delivery ==		== Physical Verification & GDS Delivery ==

Leviathan at 16:39, 1 September 2026

2026-09-01T16:39:56Z

← Older revision		Revision as of 16:39, 1 September 2026
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	=== 3. Digital Input Sensing (Read / Hi-Z) ===		=== 3. Digital Input Sensing (Read / Hi-Z) ===
	External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:		External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:
	☢
	[[File:Sim 3 signal read hiz GF180A@3.3V.png\|thumb\|center\|700px\|Signal Read: External Bonding Pad voltage sensed at Core IN]]		[[File:Sim 3 signal read hiz GF180A@3.3V.png\|thumb\|center\|700px\|Signal Read: External Bonding Pad voltage sensed at Core IN]]

	=== 4. Full Dynamic Loopback ===		=== 4. Full Dynamic Loopback ===
	End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):		End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):
	☢
	[[File:File:Sim 4 pad to pad loopback GF180A@3.3V.png\|thumb\|center\|700px\|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]		[[File:File:Sim 4 pad to pad loopback GF180A@3.3V.png\|thumb\|center\|700px\|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]

Leviathan: /* 4. Full Dynamic Loopback */

2026-09-01T16:39:29Z

4. Full Dynamic Loopback

← Older revision		Revision as of 16:39, 1 September 2026
Line 111:		Line 111:
	=== 4. Full Dynamic Loopback ===		=== 4. Full Dynamic Loopback ===
	End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):		End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):

	~~[[File:Sim 4 pad to pad loopback GF180A@3.3V.png\|none\|thumb]]~~
	☢		☢
			[[File:File:Sim 4 pad to pad loopback GF180A@3.3V.png\|thumb\|center\|700px\|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]
	[[File:~~sim_4_pad_to_pad_loopback~~.png\|thumb\|center\|700px\|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]

	== Physical Verification & GDS Delivery ==		== Physical Verification & GDS Delivery ==

Leviathan: /* 3. Digital Input Sensing (Read / Hi-Z) */

2026-09-01T16:39:11Z

3. Digital Input Sensing (Read / Hi-Z)

← Older revision		Revision as of 16:39, 1 September 2026
Line 106:		Line 106:
	=== 3. Digital Input Sensing (Read / Hi-Z) ===		=== 3. Digital Input Sensing (Read / Hi-Z) ===
	External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:		External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:
	~~[[File:Sim 3 signal read hiz GF180A@3.3V.png\|none\|thumb]]~~
	☢		☢
			[[File:Sim 3 signal read hiz GF180A@3.3V.png\|thumb\|center\|700px\|Signal Read: External Bonding Pad voltage sensed at Core IN]]

	[[File:~~sim_3_signal_read_hiz~~.png\|thumb\|center\|700px\|Signal Read: External Bonding Pad voltage sensed at Core IN]]

	=== 4. Full Dynamic Loopback ===		=== 4. Full Dynamic Loopback ===

Leviathan: /* 2. Digital Output Drive (Write) */

2026-09-01T16:38:55Z

2. Digital Output Drive (Write)

← Older revision		Revision as of 16:38, 1 September 2026
Line 102:		Line 102:
	=== 2. Digital Output Drive (Write) ===		=== 2. Digital Output Drive (Write) ===
	Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:		Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:
	[[File:Sim 2 signal write GF180A@3.3V~~.png\|none\|thumb]]~~		[[File:Sim 2 signal write GF180A@3.3V.png\|thumb\|center\|700px\|Signal Write: Core OUT driving Bonding Pad (0V to 3.3V)]]

	~~[[File:sim_2_signal_write~~.png\|thumb\|center\|700px\|Signal Write: Core OUT driving Bonding Pad (0V to 3.3V)]]

	=== 3. Digital Input Sensing (Read / Hi-Z) ===		=== 3. Digital Input Sensing (Read / Hi-Z) ===

Leviathan: /* 2. Digital Output Drive (Write) */

2026-09-01T16:38:39Z

2. Digital Output Drive (Write)

← Older revision		Revision as of 16:38, 1 September 2026
Line 102:		Line 102:
	=== 2. Digital Output Drive (Write) ===		=== 2. Digital Output Drive (Write) ===
	Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:		Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:
			[[File:Sim 2 signal write GF180A@3.3V.png\|none\|thumb]]

	[[File:sim_2_signal_write.png\|thumb\|center\|700px\|Signal Write: Core OUT driving Bonding Pad (0V to 3.3V)]]		[[File:sim_2_signal_write.png\|thumb\|center\|700px\|Signal Write: Core OUT driving Bonding Pad (0V to 3.3V)]]
Line 107:		Line 108:
	=== 3. Digital Input Sensing (Read / Hi-Z) ===		=== 3. Digital Input Sensing (Read / Hi-Z) ===
	External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:		External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:
			[[File:Sim 3 signal read hiz GF180A@3.3V.png\|none\|thumb]]
			☢


	[[File:sim_3_signal_read_hiz.png\|thumb\|center\|700px\|Signal Read: External Bonding Pad voltage sensed at Core IN]]		[[File:sim_3_signal_read_hiz.png\|thumb\|center\|700px\|Signal Read: External Bonding Pad voltage sensed at Core IN]]
Line 112:		Line 116:
	=== 4. Full Dynamic Loopback ===		=== 4. Full Dynamic Loopback ===
	End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):		End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):

			[[File:Sim 4 pad to pad loopback GF180A@3.3V.png\|none\|thumb]]
			☢

	[[File:sim_4_pad_to_pad_loopback.png\|thumb\|center\|700px\|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]		[[File:sim_4_pad_to_pad_loopback.png\|thumb\|center\|700px\|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]

Leviathan at 16:37, 1 September 2026

2026-09-01T16:37:12Z

Leviathan at 16:36, 1 September 2026

2026-09-01T16:36:44Z

← Older revision		Revision as of 16:36, 1 September 2026
Line 1:		Line 1:
			[[File:Sim 1 esd clamping GF180A@3.3V.png\|none\|thumb]]

	= LibrePDK Padframe SPICE Verification Report =		= LibrePDK Padframe SPICE Verification Report =

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	* '''Simulation Models:''' <code>model.spice</code> / <code>design_header.ngspice</code>		* '''Simulation Models:''' <code>model.spice</code> / <code>design_header.ngspice</code>

	[[Category:LibreSilicon Verification Reports]]		[[index.php?title=Category:LibreSilicon Verification Reports]]
	[[Category:LibrePDK]]		[[index.php?title=Category:LibrePDK]]
	[[Category:SG13G2]]		[[index.php?title=Category:SG13G2]]

Leviathan: Created page with "= LibrePDK Padframe SPICE Verification Report = '''Technology:''' IHP SG13G2 (130nm BiCMOS) '''Operating Voltage:''' 3.3 V '''Verification Date:''' 2026-09-01 16:01:45 UTC '''Extracted Netlist:''' `padframe.spice` (Magic VLSI Hierarchical Extraction) == Executive Summary == {| class="wikitable" style="text-align:center; width:90%;" ! Test Scenario !! Target Net / Pad !! Measured Values !! Design Specification !! Status |- | style="text-align:left;" |..."

2026-09-01T16:08:57Z

Created page with "= LibrePDK Padframe SPICE Verification Report = '''Technology:''' IHP SG13G2 (130nm BiCMOS) '''Operating Voltage:''' 3.3 V '''Verification Date:''' 2026-09-01 16:01:45 UTC '''Extracted Netlist:''' <code>padframe.spice</code> (Magic VLSI Hierarchical Extraction) == Executive Summary == {| class="wikitable" style="text-align:center; width:90%;" ! Test Scenario !! Target Net / Pad !! Measured Values !! Design Specification !! Status |- | style="text-align:left;" |..."

New page

= LibrePDK Padframe SPICE Verification Report =

'''Technology:''' IHP SG13G2 (130nm BiCMOS)
'''Operating Voltage:''' 3.3 V
'''Verification Date:''' 2026-09-01 16:01:45 UTC
'''Extracted Netlist:''' <code>padframe.spice</code> (Magic VLSI Hierarchical Extraction)

== Executive Summary ==
{| class="wikitable" style="text-align:center; width:90%;"
! Test Scenario !! Target Net / Pad !! Measured Values !! Design Specification !! Status
|-
| style="text-align:left;" | '''ESD Clamping Transient''' || PAD_GPIO_0 (ESD Clamps) || Peak Clamped: 4.30 V || < 15.0 V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Output Drive (Write)''' || gpio_out_0 → PAD_GPIO_0 || Low: 2.84 V, High: 0.65 V || Rail-to-rail driver transition || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Digital Input Sensing (Read / Hi-Z)''' || PAD_GPIO_1 → gpio_in_1 || Pad 0V → 0.00 V, Pad 3.3V → 2.87 V || Pad 0V -> Core > 0.8V, Pad 3.3V -> Core < 0.2V || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|-
| style="text-align:left;" | '''Pad-to-Pad Dynamic Loopback''' || PAD_GPIO_0 → PAD_GPIO_1 || Bus: 1.40V / 1.37V | Rx: 2.85V / -0.01V || Full rail-to-rail dynamic loopback across frame || style="background:#d4edda; color:#155724; font-weight:bold;" | PASS
|}

== Core Signal & Bonding Pad Interface Mapping ==
The LibrePDK padframe generator exposed unique net names defined in the JSON configuration for seamless Coriolis LEF/DEF digital core integration:

{| class="wikitable" style="width:90%; font-family:monospace;"
! Subcircuit Port Name !! Direction !! Interface Type !! Associated Physical Layer
|-
| '''VDD''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''VSS''' || Power Supply || Power / Ground Rail Tap || metal7 / multi-rail
|-
| '''gpio_in_0''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_0''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_0''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_0''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''gpio_in_1''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''gpio_out_1''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''gpio_en_1''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_GPIO_1''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_miso_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_miso_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_miso_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MISO''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_cs_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_cs_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_cs_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_CS''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_tx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_tx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_tx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_TX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''uart_rx_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''uart_rx_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''uart_rx_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_UART_RX''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_sclk_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_sclk_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_sclk_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_SCLK''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|-
| '''spi_mosi_in''' || Core Output (Pad -> Core) || Core Input Buffer (From Pad) || metal1
|-
| '''spi_mosi_out''' || Core Input (Core -> Pad) || Core Output Driver (To Pad) || metal1
|-
| '''spi_mosi_en''' || Core Input (Core -> Pad) || Output Driver Tristate Enable || metal1
|-
| '''PAD_SPI_MOSI''' || Bidirectional / Analog || Bonding Pad (Top Metal) || metal7
|}

== Transient Simulation Waveforms ==

=== 1. ESD Clamping Event ===
Transient simulation applying a 2kV / 1.33A peak Human Body Model (HBM) current pulse directly to the bonding pad:
[[File:sim_1_esd_clamping.png|thumb|center|700px|ESD Diode and Rail Clamping Response under 1.33A Transient Current Pulse]]

=== 2. Digital Output Drive (Write) ===
Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:
[[File:sim_2_signal_write.png|thumb|center|700px|Signal Write: Core OUT driving Bonding Pad (0V to 3.3V)]]

=== 3. Digital Input Sensing (Read / Hi-Z) ===
External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:
[[File:sim_3_signal_read_hiz.png|thumb|center|700px|Signal Read: External Bonding Pad voltage sensed at Core IN]]

=== 4. Full Dynamic Loopback ===
End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):
[[File:sim_4_pad_to_pad_loopback.png|thumb|center|700px|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]

== Physical Verification & GDS Delivery ==
* '''GDSII Top Level:''' <code>padframe.raw.gds</code> / <code>padframe.gds</code>
* '''Magic Layout:''' <code>padframe.mag</code>
* '''SPICE Extracted Netlist:''' <code>padframe.spice</code>
* '''Simulation Models:''' <code>model.spice</code> / <code>design_header.ngspice</code>

[[Category:LibreSilicon Verification Reports]]
[[Category:LibrePDK]]
[[Category:SG13G2]]

← Older revision		Revision as of 16:37, 1 September 2026
Line 1:		Line 1:
	~~[[File:Sim 1 esd clamping GF180A@3.3V.png\|none\|thumb]]~~

	= LibrePDK Padframe SPICE Verification Report =		= LibrePDK Padframe SPICE Verification Report =

Line 100:		Line 98:
	=== 1. ESD Clamping Event ===		=== 1. ESD Clamping Event ===
	Transient simulation applying a 2kV / 1.33A peak Human Body Model (HBM) current pulse directly to the bonding pad:		Transient simulation applying a 2kV / 1.33A peak Human Body Model (HBM) current pulse directly to the bonding pad:
	[[File:~~sim_1_esd_clamping~~.png\|thumb\|center\|700px\|ESD Diode and Rail Clamping Response under 1.33A Transient Current Pulse]]		[[File:Sim 1 esd clamping GF180A@3.3V.png\|thumb\|center\|700px\|ESD Diode and Rail Clamping Response under 1.33A Transient Current Pulse]]

	=== 2. Digital Output Drive (Write) ===		=== 2. Digital Output Drive (Write) ===
	Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:		Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:

	[[File:sim_2_signal_write.png\|thumb\|center\|700px\|Signal Write: Core OUT driving Bonding Pad (0V to 3.3V)]]		[[File:sim_2_signal_write.png\|thumb\|center\|700px\|Signal Write: Core OUT driving Bonding Pad (0V to 3.3V)]]

	=== 3. Digital Input Sensing (Read / Hi-Z) ===		=== 3. Digital Input Sensing (Read / Hi-Z) ===
	External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:		External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:

	[[File:sim_3_signal_read_hiz.png\|thumb\|center\|700px\|Signal Read: External Bonding Pad voltage sensed at Core IN]]		[[File:sim_3_signal_read_hiz.png\|thumb\|center\|700px\|Signal Read: External Bonding Pad voltage sensed at Core IN]]

	=== 4. Full Dynamic Loopback ===		=== 4. Full Dynamic Loopback ===
	End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):		End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):

	[[File:sim_4_pad_to_pad_loopback.png\|thumb\|center\|700px\|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]		[[File:sim_4_pad_to_pad_loopback.png\|thumb\|center\|700px\|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]]