LibreSilicon stack - Revision history

Leviathan: /* Pad Frames */

2026-08-31T08:26:20Z

Pad Frames

← Older revision		Revision as of 08:26, 31 August 2026
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	=== Pad Frames ===		=== Pad Frames ===
	The [[Pad Frame Generator]] has the job of taking in a JSON with pin assignment for the East, North, South and West bank and then calculate the wire dimensions of the overall padframe based on the projected peak currents as well as to choose the right pad cell type for each assigned pin.		The [[Pad Frame Generator]] has the job of taking in a JSON with pin assignment for the East, North, South and West bank and then calculate the wire dimensions of the overall padframe based on the projected peak currents as well as to choose the right pad cell type for each assigned pin.
	[[File:~~Pad Frame v2~~ Example ~~SG13G2@1V2~~.png\|none\|thumb\|Pad Frame Example SG13G2@1.2V]]		[[File:Padframe Example.png\|none\|thumb\|Pad Frame Example SG13G2@1.2V]]
	The resulting output will be a pad frame in Magic, GDS2, LEF and DEF format, which you can use for placing and routing your internal logic to.		The resulting output will be a pad frame in Magic, GDS2, LEF and DEF format, which you can use for placing and routing your internal logic to.

Leviathan: /* Pad Cells */

2026-08-31T08:17:10Z

Pad Cells

← Older revision		Revision as of 08:17, 31 August 2026
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	=== Pad Cells ===		=== Pad Cells ===
	The [[Pad Cell Generator]] is part of the [[LibrePDK]] and can be used to created custom sets of pad cells with custom rail voltages and you can even define a set of currents your pad frame is supposed to end up driving.		The [[Pad Cell Generator]] is part of the [[LibrePDK]] and can be used to created custom sets of pad cells with custom rail voltages and you can even define a set of currents your pad frame is supposed to end up driving.
	[[File:~~30mA SG13G2@1V2 v2~~.png\|none\|thumb\|~~419x419px\|30mA pad cell for IHPSG13G2 at 1.2V~~]]		[[File:Sg13g2 1v2 io cell 60mA 1p2V.png\|none\|thumb\|padframe_sg13g2_1v2/io_cell_60mA_1p2V/]]
	The pad cell has such thin wires, because the ultimate wire width has to be determined based on the final current which is supposed to be driven by the overall pad frame the cells are being generated for.		The pad cell has such thin wires, because the ultimate wire width has to be determined based on the final current which is supposed to be driven by the overall pad frame the cells are being generated for.
	=== Pad Frames ===		=== Pad Frames ===

Leviathan: /* Standard Cells */

2026-08-08T17:16:28Z

Standard Cells

← Older revision		Revision as of 17:16, 8 August 2026
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	You need standard logic cells, small logic gate layouts made from place and routing discrete FETs, in order to turn the RTL level logic Yosys spits out into an actual digital chip layout.		You need standard logic cells, small logic gate layouts made from place and routing discrete FETs, in order to turn the RTL level logic Yosys spits out into an actual digital chip layout.

			You can now use the [[LibreStandardCell]] generator and generate custom standard logic cell libraries where you decide the target technology, voltage, height and thermal budget.
			[[File:LibreStandardCell screeny2.png\|none\|thumb]]
	Originally Philip was working on [[StdCellLib]], but he re-licensed it under Apache which kind of defeats the purpose of a project calling itself '''Libre'''Silicon. Because Leviathan was a bit triggered by this due to his definition of Libre being the same as the Free Software Foundation, which means, that it's supposed under a GNU Public License, he decided to work on introducing the functionality for placing and routing standard logic cells in [[LibrePDK]] as well, in addition to analog and pad cell generation.		Originally Philip was working on [[StdCellLib]], but he re-licensed it under Apache which kind of defeats the purpose of a project calling itself '''Libre'''Silicon. Because Leviathan was a bit triggered by this due to his definition of Libre being the same as the Free Software Foundation, which means, that it's supposed under a GNU Public License, he decided to work on introducing the functionality for placing and routing standard logic cells in [[LibrePDK]] as well, in addition to analog and pad cell generation.

	~~You can now use the [[LibreStandardCell]] generator and generate custom standard logic cell libraries where you decide the target technology, voltage, height and thermal budget.~~

	=== Pad Cells ===		=== Pad Cells ===

Leviathan: /* Standard Cells */

2026-08-08T12:46:44Z

Standard Cells

← Older revision		Revision as of 12:46, 8 August 2026
Line 15:		Line 15:

	Originally Philip was working on [[StdCellLib]], but he re-licensed it under Apache which kind of defeats the purpose of a project calling itself '''Libre'''Silicon. Because Leviathan was a bit triggered by this due to his definition of Libre being the same as the Free Software Foundation, which means, that it's supposed under a GNU Public License, he decided to work on introducing the functionality for placing and routing standard logic cells in [[LibrePDK]] as well, in addition to analog and pad cell generation.		Originally Philip was working on [[StdCellLib]], but he re-licensed it under Apache which kind of defeats the purpose of a project calling itself '''Libre'''Silicon. Because Leviathan was a bit triggered by this due to his definition of Libre being the same as the Free Software Foundation, which means, that it's supposed under a GNU Public License, he decided to work on introducing the functionality for placing and routing standard logic cells in [[LibrePDK]] as well, in addition to analog and pad cell generation.

			You can now use the [[LibreStandardCell]] generator and generate custom standard logic cell libraries where you decide the target technology, voltage, height and thermal budget.

	=== Pad Cells ===		=== Pad Cells ===

Leviathan: /* Pad Cells */

2026-05-29T09:37:56Z

Pad Cells

← Older revision		Revision as of 09:37, 29 May 2026
Line 18:		Line 18:
	=== Pad Cells ===		=== Pad Cells ===
	The [[Pad Cell Generator]] is part of the [[LibrePDK]] and can be used to created custom sets of pad cells with custom rail voltages and you can even define a set of currents your pad frame is supposed to end up driving.		The [[Pad Cell Generator]] is part of the [[LibrePDK]] and can be used to created custom sets of pad cells with custom rail voltages and you can even define a set of currents your pad frame is supposed to end up driving.
	[[File:~~Io cell 20mA~~.png\|none\|thumb\|~~20mA~~ pad cell for IHPSG13G2 at 1.2V]]		[[File:30mA SG13G2@1V2 v2.png\|none\|thumb\|419x419px\|30mA pad cell for IHPSG13G2 at 1.2V]]
	The pad cell has such thin wires, because the ultimate wire width has to be determined based on the final current which is supposed to be driven by the overall pad frame the cells are being generated for.		The pad cell has such thin wires, because the ultimate wire width has to be determined based on the final current which is supposed to be driven by the overall pad frame the cells are being generated for.
	=== Pad Frames ===		=== Pad Frames ===

Leviathan: /* Pad Frames */

2026-05-29T09:28:30Z

Pad Frames

← Older revision		Revision as of 09:28, 29 May 2026
Line 21:		Line 21:
	The pad cell has such thin wires, because the ultimate wire width has to be determined based on the final current which is supposed to be driven by the overall pad frame the cells are being generated for.		The pad cell has such thin wires, because the ultimate wire width has to be determined based on the final current which is supposed to be driven by the overall pad frame the cells are being generated for.
	=== Pad Frames ===		=== Pad Frames ===
	The [[Pad Frame Generator]] has the job of taking in a JSON with pin assignment for the East, North, South and West bank and then calculate the wire dimensions of the overall padframe based on the projected peak currents as well as to choose the right pad cell type for each assigned pin.[[File:~~Preliminary First~~ Pad Frame ~~generated~~.png\|thumb\|~~An example of an early result of LibrePDK\|none~~]]		The [[Pad Frame Generator]] has the job of taking in a JSON with pin assignment for the East, North, South and West bank and then calculate the wire dimensions of the overall padframe based on the projected peak currents as well as to choose the right pad cell type for each assigned pin.
			[[File:Pad Frame v2 Example SG13G2@1V2.png\|none\|thumb\|Pad Frame Example SG13G2@1.2V]]
	The resulting output will be a pad frame in Magic, GDS2, LEF and DEF format, which you can use for placing and routing your internal logic to.		The resulting output will be a pad frame in Magic, GDS2, LEF and DEF format, which you can use for placing and routing your internal logic to.

Leviathan: /* Pad Cells */

2026-05-28T16:15:04Z

Pad Cells

← Older revision		Revision as of 16:15, 28 May 2026
Line 18:		Line 18:
	=== Pad Cells ===		=== Pad Cells ===
	The [[Pad Cell Generator]] is part of the [[LibrePDK]] and can be used to created custom sets of pad cells with custom rail voltages and you can even define a set of currents your pad frame is supposed to end up driving.		The [[Pad Cell Generator]] is part of the [[LibrePDK]] and can be used to created custom sets of pad cells with custom rail voltages and you can even define a set of currents your pad frame is supposed to end up driving.
			[[File:Io cell 20mA.png\|none\|thumb\|20mA pad cell for IHPSG13G2 at 1.2V]]
			The pad cell has such thin wires, because the ultimate wire width has to be determined based on the final current which is supposed to be driven by the overall pad frame the cells are being generated for.
	=== Pad Frames ===		=== Pad Frames ===
	[[File:Preliminary First Pad Frame generated.png\|thumb\|An example of an early result of LibrePDK\|none]]		The [[Pad Frame Generator]] has the job of taking in a JSON with pin assignment for the East, North, South and West bank and then calculate the wire dimensions of the overall padframe based on the projected peak currents as well as to choose the right pad cell type for each assigned pin.[[File:Preliminary First Pad Frame generated.png\|thumb\|An example of an early result of LibrePDK\|none]]


			The resulting output will be a pad frame in Magic, GDS2, LEF and DEF format, which you can use for placing and routing your internal logic to.

	==Physical manufacturing==		==Physical manufacturing==

Leviathan: /* Pad Cells */

2026-05-28T16:11:19Z

Pad Cells

← Older revision		Revision as of 16:11, 28 May 2026
Line 17:		Line 17:

	=== Pad Cells ===		=== Pad Cells ===
	~~[[File:Preliminary First Pad Frame generated.png\|thumb\|An example of an early result of LibrePDK\|none]]~~
	The [[Pad Cell Generator]] is part of the [[LibrePDK]] and can be used to created custom sets of pad cells with custom rail voltages and you can even define a set of currents your pad frame is supposed to end up driving.		The [[Pad Cell Generator]] is part of the [[LibrePDK]] and can be used to created custom sets of pad cells with custom rail voltages and you can even define a set of currents your pad frame is supposed to end up driving.


	=== Pad Frames ===		=== Pad Frames ===
			[[File:Preliminary First Pad Frame generated.png\|thumb\|An example of an early result of LibrePDK\|none]]



	==Physical manufacturing==		==Physical manufacturing==

Leviathan at 16:10, 28 May 2026

2026-05-28T16:10:42Z

← Older revision		Revision as of 16:10, 28 May 2026
Line 17:		Line 17:

	=== Pad Cells ===		=== Pad Cells ===
	[[File:Preliminary First Pad Frame generated.png\|thumb\|An example of an early result of LibrePDK]]		[[File:Preliminary First Pad Frame generated.png\|thumb\|An example of an early result of LibrePDK\|none]]
	The [[Pad Cell Generator]] is part of the [[LibrePDK]] and can be used to created custom sets of pad cells with custom rail voltages and you can even define a set of currents your pad frame is supposed to end up driving.		The [[Pad Cell Generator]] is part of the [[LibrePDK]] and can be used to created custom sets of pad cells with custom rail voltages and you can even define a set of currents your pad frame is supposed to end up driving.

			=== Pad Frames ===

	==Physical manufacturing==		==Physical manufacturing==

Leviathan: /* Pad Cells */

2026-05-25T21:58:57Z

Pad Cells

← Older revision		Revision as of 21:58, 25 May 2026
Line 12:		Line 12:

	=== Standard Cells ===		=== Standard Cells ===
	~~TODO: More text~~		You need standard logic cells, small logic gate layouts made from place and routing discrete FETs, in order to turn the RTL level logic Yosys spits out into an actual digital chip layout.

	[[StdCellLib]]		Originally Philip was working on [[StdCellLib]], but he re-licensed it under Apache which kind of defeats the purpose of a project calling itself '''Libre'''Silicon. Because Leviathan was a bit triggered by this due to his definition of Libre being the same as the Free Software Foundation, which means, that it's supposed under a GNU Public License, he decided to work on introducing the functionality for placing and routing standard logic cells in [[LibrePDK]] as well, in addition to analog and pad cell generation.

	=== Pad Cells ===		=== Pad Cells ===
	~~TODO~~: ~~More text~~		[[File:Preliminary First Pad Frame generated.png\|thumb\|An example of an early result of LibrePDK]]
			The [[Pad Cell Generator]] is part of the [[LibrePDK]] and can be used to created custom sets of pad cells with custom rail voltages and you can even define a set of currents your pad frame is supposed to end up driving.
	[[Pad Cell Generator]]

	==Physical manufacturing==		==Physical manufacturing==