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Created page with "Highway is the LibreSilicon VLSI project manager which helps you easily manage multiple Verilog and HDL projects, add them to a die, configure a padframe and run a complete synthesis flow using LibrePDK and Coriolis. Simply create a Python 3.12 environment and install the tool with pip<syntaxhighlight lang="bash"> python3.12 -m venv venv . venv/bin/activate pip install git+https://gitlab.libresilicon.com/leviathan/highway </syntaxhighlight>" |
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Highway is the LibreSilicon VLSI project manager which helps you easily manage multiple Verilog and HDL projects, add them to a die, configure a padframe and run a complete synthesis flow using LibrePDK and Coriolis. | Highway is the LibreSilicon VLSI project manager which helps you easily manage multiple Verilog and HDL projects, add them to a die, configure a padframe and run a complete synthesis flow using [[LibrePDK]] and [https://coriolis.lip6.fr Coriolis]. | ||
Simply create a Python 3.12 environment and install the tool with pip<syntaxhighlight lang="bash"> | Simply create a Python 3.12 environment and install the tool with pip<syntaxhighlight lang="bash"> | ||
apt update | |||
apt install g++ git yosys ngspice python3-pip | |||
python3.12 -m venv venv | python3.12 -m venv venv | ||
. venv/bin/activate | . venv/bin/activate | ||
pip install git+https://gitlab.libresilicon.com/leviathan/highway | pip install git+https://gitlab.libresilicon.com/leviathan/highway | ||
</syntaxhighlight> | </syntaxhighlight> | ||
== Test dies == | |||
Below a list of links to test die tapeouts for validating the [[Pad Frame Generator]] and [[StdCellLib CellLibraries]] generator with manufacturing nodes and technologies. | |||
* [[Test Die SG13G2@1.2V]] | |||
Latest revision as of 05:17, 26 October 2026
Highway is the LibreSilicon VLSI project manager which helps you easily manage multiple Verilog and HDL projects, add them to a die, configure a padframe and run a complete synthesis flow using LibrePDK and Coriolis.
Simply create a Python 3.12 environment and install the tool with pip
apt update
apt install g++ git yosys ngspice python3-pip
python3.12 -m venv venv
. venv/bin/activate
pip install git+https://gitlab.libresilicon.com/leviathan/highway
Test dies
Below a list of links to test die tapeouts for validating the Pad Frame Generator and StdCellLib CellLibraries generator with manufacturing nodes and technologies.