StdCellLib

The Standard Cell Library generator has the function of generating a set of logic gates for any given VLSI process node by feeding it the relevant design rules for calculating the dimension and performing the place and route of the relevant transistors, so that a layout can be generated using the synthesis flow provided by OpenROAD.

The development of this tool has been mainly funded by NLNet (https://nlnet.nl/project/LibreSiliconStandardCellLibrary/) as well as Google.

An overview of all the cells available for generation can be found here: StdCellLib CellLibraries

Running the generator

First clone the repository

git clone https://github.com/thesourcerer8/StdCellLib.git
cd StdCellLib.git

Then you fetch the Dockerimage with all the LibreSilicon tools preinstalled, just as with DanubeRiver:

docker pull leviathanch/libresilicon-tools:latest

Then you've got to start the Docker container and build the standard cell library for your specific process

xhost +local:docker
docker run -e DISPLAY=$DISPLAY -v /tmp/.X11-unix:/tmp/.X11-unix -v `pwd`:/work -it leviathanch/libresilicon-tools
cd Catalog
make layout

Your resulting GDS2 files and other library formats can afterwards be found in "/work/Catalog/outputlib"