ESD Verification: Difference between revisions

Latest revision as of 13:37, 29 May 2026

Below two examples from our automated test suite showcasing how our approach reverse solving the HBM model math as elaborated in Physics-Based_Wire_Sizing_for_I/O_Pad_Cells actually leads to simulation results in ngspice which show that our ESD diodes we chose actually protect our internal circuitry.

Oh wow. When you solve Ohm's law in one direction and then the other, you end up with the current you originally have defined at a certain voltage. Who would have thought this... anyway. Here some examples.

After running

./tests/test_all_padcells.sh

you end up with a folder called "generated_output"

We're looking at "generated_output/SG13G2/padcell/1.2V" and "generated_output/SG13G2/padcell/3.3V" here as examples

As described here the test setup is really simple:

The deck models a basic HBM discharge setup with:

a 100 pF capacitor
a 1.5 kΩ series resistor
a switched discharge path

This is just the driver stage test. The input buffer will be having additional tests

ESD Tests

The energy which would otherwise go through the internal digital logic takes the alternative path of least resistance, which is the two diodes (we're not generating Schottky diodes yet, see the list of devices in LibrePDK), which we put as close to the bonding pad as possible.

Here are the SPICE decks

Here a quick drawing to illustrate the configuration.

Running the detailed tests for IHP with

./tests/run_single_test.sh SG13G2:1.2 padcell

yields

Peak PAD voltage: 2.467 V
Peak current: 1.330122 A
Peak resistor power: 2.654 kW
Final dissipated energy: 168.225485 µJ
HBM plots written to /run/media/leviathan/dde9e2a1-4a6e-4d1b-afec-7c557d080ef8/LibrePDK/librepdk/generated_output/SG13G2/1.2V/padcell/out/io_cell_20mA_1p2V/plots/hbm_pd_forward
Waveform data: /run/media/leviathan/dde9e2a1-4a6e-4d1b-afec-7c557d080ef8/LibrePDK/librepdk/generated_output/SG13G2/1.2V/padcell/out/io_cell_20mA_1p2V/hbm_waveforms_hbm_pd_forward.dat
Peak PAD voltage: 2.310 V
Peak current: 1.330248 A
Peak resistor power: 2.654 kW
Final dissipated energy: 168.240327 µJ
HBM plots written to /run/media/leviathan/dde9e2a1-4a6e-4d1b-afec-7c557d080ef8/LibrePDK/librepdk/generated_output/SG13G2/1.2V/padcell/out/io_cell_20mA_1p2V/plots/hbm_ns_forward
Waveform data: /run/media/leviathan/dde9e2a1-4a6e-4d1b-afec-7c557d080ef8/LibrePDK/librepdk/generated_output/SG13G2/1.2V/padcell/out/io_cell_20mA_1p2V/hbm_waveforms_hbm_ns_forward.dat
Peak PAD voltage: -0.029 V
Peak current: 1.323457 A
Peak resistor power: 2.627 kW
Final dissipated energy: 166.729178 µJ
HBM plots written to /run/media/leviathan/dde9e2a1-4a6e-4d1b-afec-7c557d080ef8/LibrePDK/librepdk/generated_output/SG13G2/1.2V/padcell/out/io_cell_20mA_1p2V/plots/hbm_nd_reverse
Waveform data: /run/media/leviathan/dde9e2a1-4a6e-4d1b-afec-7c557d080ef8/LibrePDK/librepdk/generated_output/SG13G2/1.2V/padcell/out/io_cell_20mA_1p2V/hbm_waveforms_hbm_nd_reverse.dat
Peak PAD voltage: -0.029 V
Peak current: 1.323461 A
Peak resistor power: 2.627 kW
Final dissipated energy: 166.782671 µJ

HBS Forward

Simulating forward ESD discharge basically simulates the path drawn below

The forward discharge results in a cummulative energy of 100-150 micro Jules.

The things won't even get warm

HBS Reverse

For the reverse test, it's backwards...

The same graph results from simulating the reverse ESD, because that's how the diodes have been dimensioned

Not matter which direction, things won't even get warm

The IHP SG13G2 case

Comparing those two you will notice that the pad with the lower operational voltage needs more area.

While at first counter intuitive, this is because we're not dealing with Ohm's law here but with solid state physics, such as hot carriers and the such.

It's a balance between electron mobility and thermal budget... took a while to code that. It's really complicated physics, but it's now all done in Python so you won't have to solve those partial differential equations yourself.

Lets look at those two pad cells here. One is dimensionsed for 30mA at 1.2V and the other at 3.3V

One would assume that the 3.3V transistors would be larger.

However.

The width of a channel (length of the gate) is being determined by $L_{g a t e} = I_{t a r g e t} / I_{s a t}$ with $[I_{s a t}] = \frac{m A}{u A}$

That however has to be combined with the thermal budget, which gives a minimum area for the energy to be dissipated on.

In the case of the 1.2V transistors the saturation current of the channel isn't high enough anyway for violating the minimum area requirement because it doesn't have additional doping like the IHP transistor lifted to 3.3V by additional HV doping.

This doping improves the conductivity of the channel, so the gates had to be scaled up in order to cover enough space for dissipating the energy they conduct.

@@ Line 4: / Line 4: @@
 After running<syntaxhighlight lang="bash">
-./tests/test_all_padcells.sh visual
+./tests/test_all_padcells.sh
 </syntaxhighlight>you end up with a folder called "generated_output"
@@ Line 16: / Line 16: @@
 * a 1.5 kΩ series resistor
 * a switched discharge path
-* a bias on <code>NOT_EN</code> so the driver remains disabled during the pulse
 This is just the driver stage test. The input buffer will be having additional tests
-== ESD path: Bonding Path to VSS ESD and VDD ESD ==
+== ESD Tests ==
 The energy which would otherwise go through the internal digital logic takes the alternative path of least resistance, which is the two diodes (we're not generating Schottky diodes yet, see the list of devices in [[LibrePDK]]), which we put as close to the bonding pad as possible.
+Here are the [https://gitlab.libresilicon.com/generator-tools/librepdk/-/tree/master/tests/esd?ref_type=heads SPICE decks]
 Here a quick drawing to illustrate the configuration.
-[[File:PAD-VDD-VSS ESD path.png|none|thumb|200x200px]]
+[[File:PAD-VDD-VSS ESD path.png|none|thumb|200x200px]]Running the detailed tests for IHP with<syntaxhighlight lang="bash">
-Inthe case of IHP SG13G2 @ 1.2V the discharge simulation looks like plotted below.
+./tests/run_single_test.sh SG13G2:1.2 padcell
+</syntaxhighlight>yields<syntaxhighlight lang="bash">
-Here are some simulation values extracted from ngspice
+Peak PAD voltage: 2.467 V
+Peak current: 1.330122 A
-* '''Peak PAD voltage:''' 1910.869 V
+Peak resistor power: 2.654 kW
-* '''Peak current:''' 1.314834 A
+Final dissipated energy: 168.225485 µJ
-* '''Peak resistor power:''' 2.593 kW  That's over a 1.5 kΩ sense resistor, the power dissipated over the actual diodes is is only 3.144856 µJ
+HBM plots written to /run/media/leviathan/dde9e2a1-4a6e-4d1b-afec-7c557d080ef8/LibrePDK/librepdk/generated_output/SG13G2/1.2V/padcell/out/io_cell_20mA_1p2V/plots/hbm_pd_forward
-* '''Final dissipated energy:''' 3.144856 µJ
+Waveform data: /run/media/leviathan/dde9e2a1-4a6e-4d1b-afec-7c557d080ef8/LibrePDK/librepdk/generated_output/SG13G2/1.2V/padcell/out/io_cell_20mA_1p2V/hbm_waveforms_hbm_pd_forward.dat
+Peak PAD voltage: 2.310 V
-==== HBM ESD Dissipation ====
+Peak current: 1.330248 A
-Assuming a typical ESD discharge of a few nanoseconds the energy absorbed by the chip itself is in the '''micro''' Jules range (3.144856 µJ)
+Peak resistor power: 2.654 kW
+Final dissipated energy: 168.240327 µJ
-That's nothing
+HBM plots written to /run/media/leviathan/dde9e2a1-4a6e-4d1b-afec-7c557d080ef8/LibrePDK/librepdk/generated_output/SG13G2/1.2V/padcell/out/io_cell_20mA_1p2V/plots/hbm_ns_forward
-[[File:HBM ESD dissipation SG13G2@1.2V.png|none|thumb]]
+Waveform data: /run/media/leviathan/dde9e2a1-4a6e-4d1b-afec-7c557d080ef8/LibrePDK/librepdk/generated_output/SG13G2/1.2V/padcell/out/io_cell_20mA_1p2V/hbm_waveforms_hbm_ns_forward.dat
+Peak PAD voltage: -0.029 V
-==== ESD Waveforms ====
+Peak current: 1.323457 A
-The current flowing through the pad during an ESD event is only 2100 * 1e-10 at its peak.
+Peak resistor power: 2.627 kW
+Final dissipated energy: 166.729178 µJ
+HBM plots written to /run/media/leviathan/dde9e2a1-4a6e-4d1b-afec-7c557d080ef8/LibrePDK/librepdk/generated_output/SG13G2/1.2V/padcell/out/io_cell_20mA_1p2V/plots/hbm_nd_reverse
+Waveform data: /run/media/leviathan/dde9e2a1-4a6e-4d1b-afec-7c557d080ef8/LibrePDK/librepdk/generated_output/SG13G2/1.2V/padcell/out/io_cell_20mA_1p2V/hbm_waveforms_hbm_nd_reverse.dat
+Peak PAD voltage: -0.029 V
+Peak current: 1.323461 A
+Peak resistor power: 2.627 kW
+Final dissipated energy: 166.782671 µJ
-You can see how the voltage on the bonding pad drops while the current and power stays very small[[File:Hbm esd waveforms.png|none|thumb|335x335px]]
+</syntaxhighlight>
-*0.1nA = 210nA = 0.2uA  ... high ohmic inputs when being turned off are doing high ohmic things.
-Just as dimensionsed, the ESD protection does its job
+=== HBS Forward ===
+Simulating forward ESD discharge basically simulates the path drawn below
+[[File:ESD forward IHP SG13G2 1V2.png|thumb|277x277px|none]]The forward discharge results in a cummulative energy of 100-150 micro Jules.
+[[File:Forward Hbm esd dissipation.png|none|thumb]]
+The things won't even get warm
-Only in the beginning there's a huge peak in current 1.314834 A, but since it's only a burst of a few nano seconds the ESD diodes handle it with ease
+=== HBS Reverse ===
+For the reverse test, it's backwards...
+[[File:ESD backwards IHP SG13G2-@ 1v2.png|none|thumb|341x341px]]The same graph results from simulating the reverse ESD, because that's how the diodes have been dimensioned
+[[File:Reverse Hbm esd dissipation.png|none|thumb]]
+Not matter which direction, things won't even get warm
-== ESD path from bonding to internal logic ==
+== The IHP SG13G2 case ==
-The second test is the simulation of whether we have a calculated break through between the external bonding pad and the internal GPIO logic going into the digital core logic (center of the die)
-[[File:ESD path from outside to internal.png|none|thumb]]
-As you can see (hopefully) in the drawing I quickly made here in my KolourPaint, we simulate the ESD breakthrough path, which is expected to be negligible due to our backwards calculation, from the outside pad based on the Human Body Model through the pad cell, through the digital logic to ground.
-=== The IHP SG13G2 case ===
 Comparing those two you will notice that the pad with the lower operational voltage needs more area.
@@ Line 69: / Line 79: @@
 However.
-The width of a channel (length of the gate) is being determined by <math>L_{gate} = I_{target}/I_{sat}</math>
+The width of a channel (length of the gate) is being determined by <math display="inline">L_{gate} = I_{target}/I_{sat}</math> with <math>\left [ I_{sat} \right ] = \frac{mA}{uA} </math>
+That however has to be combined with the thermal budget, which gives a minimum area for the energy to be dissipated on.
+In the case of the 1.2V transistors the saturation current of the channel isn't high enough anyway for violating the minimum area requirement because it doesn't have additional doping like the IHP transistor lifted to 3.3V by additional HV doping.
+This doping improves the conductivity of the channel, so the gates had to be scaled up in order to cover enough space for dissipating the energy they conduct.

ESD Verification: Difference between revisions

Latest revision as of 13:37, 29 May 2026

Contents

ESD Tests

HBS Forward

HBS Reverse

The IHP SG13G2 case

Navigation menu

ESD Verification: Difference between revisions

Latest revision as of 13:37, 29 May 2026

ESD Tests

HBS Forward

HBS Reverse

The IHP SG13G2 case

Navigation menu

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