ESD Verification

Below two examples from our automated test suite showcasing how our approach reverse solving the HBM model math as elaborated in Physics-Based_Wire_Sizing_for_I/O_Pad_Cells actually leads to simulation results in ngspice which show that our ESD diodes we chose actually protect our internal circuitry.

Oh wow. When you solve Ohm's law in one direction and then the other, you end up with the current you originally have defined at a certain voltage. Who would have thought this... anyway. Here some examples.

After running

./tests/test_all_padcells.sh visual

you end up with a folder called "generated_output"

We're looking at "generated_output/SG13G2/padcell/1.2V" and "generated_output/SG13G2/padcell/3.3V" here as examples

As described here the test setup is really simple:

The deck models a basic HBM discharge setup with:

• a 100 pF capacitor
• a 1.5 kΩ series resistor
• a switched discharge path
• a bias on NOT_EN so the driver remains disabled during the pulse

This is just the driver stage test. The input buffer will be having additional tests

ESD path: Bonding Path to VSS ESD and VDD ESD

The energy which would otherwise go through the internal digital logic takes the alternative path of least resistance, which is the two diodes (we're not generating Schottky diodes yet, see the list of devices in LibrePDK), which we put as close to the bonding pad as possible.

Here a quick drawing to illustrate the configuration.

Inthe case of IHP SG13G2 @ 1.2V the discharge simulation looks like plotted below.

Here are some simulation values extracted from ngspice

• Peak PAD voltage: 1910.869 V
• Peak current: 1.314834 A
• Peak resistor power: 2.593 kW That's over a 1.5 kΩ sense resistor, the power dissipated over the actual diodes is is only 3.144856 µJ
• Final dissipated energy: 3.144856 µJ

HBM ESD Dissipation

Assuming a typical ESD discharge of a few nanoseconds the energy absorbed by the chip itself is in the micro Jules range (3.144856 µJ)

That's nothing

ESD Waveforms

The current flowing through the pad during an ESD event is only 2100 * 1e-10 at its peak.

You can see how the voltage on the bonding pad drops while the current and power stays very small

2100*0.1nA = 210nA = 0.2uA ... high ohmic inputs when being turned off are doing high ohmic things.

Just as dimensionsed, the ESD protection does its job

Only in the beginning there's a huge peak in current 1.314834 A, but since it's only a burst of a few nano seconds the ESD diodes handle it with ease

ESD path from bonding to internal logic

The second test is the simulation of whether we have a calculated break through between the external bonding pad and the internal GPIO logic going into the digital core logic (center of the die)

As you can see (hopefully) in the drawing I quickly made here in my KolourPaint, we simulate the ESD breakthrough path, which is expected to be negligible due to our backwards calculation, from the outside pad based on the Human Body Model through the pad cell, through the digital logic to ground.

The IHP SG13G2 case

Comparing those two you will notice that the pad with the lower operational voltage needs more area.

While at first counter intuitive, this is because we're not dealing with Ohm's law here but with solid state physics, such as hot carriers and the such.

It's a balance between electron mobility and thermal budget... took a while to code that. It's really complicated physics, but it's now all done in Python so you won't have to solve those partial differential equations yourself.

30mA SG13G2@1V2

30mA SG13G2@3V3

Lets look at those two pad cells here. One is dimensionsed for 30mA at 1.2V and the other at 3.3V

One would assume that the 3.3V transistors would be larger.

However.

The width of a channel (length of the gate) is being determined by $L_{gate}=I_{target}/I_{sat}$