LibrePDK Padframe SPICE Verification Report SG13G2@1.2V: Difference between revisions
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Created page with "= LibrePDK Padframe SPICE Verification Report = '''Technology:''' IHP SG13G2 (130nm BiCMOS) '''Operating Voltage:''' 1.2 V '''Verification Date:''' 2026-09-01 16:47:40 UTC '''Extracted Netlist:''' <code>padframe.spice</code> (Magic VLSI Hierarchical Extraction) == Executive Summary == {| class="wikitable" style="text-align:center; width:90%;" ! Test Scenario !! Target Net / Pad !! Measured Values !! Design Specification !! Status |- | style="text-align:left;" |..." |
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End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B): | End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B): | ||
[[File:sim_4_pad_to_pad_loopback.png|thumb|center|700px|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]] | [[File:sim_4_pad_to_pad_loopback.png|thumb|center|700px|Pad-to-Pad Dynamic Loopback: Transmitter OUT to Receiver IN]] | ||
[[File:Sim 4 pad to pad loopback SG13G2@1.2V.png|none|thumb]] | |||
== Physical Verification & GDS Delivery == | == Physical Verification & GDS Delivery == | ||
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* '''Simulation Models:''' <code>model.spice</code> / <code>design_header.ngspice</code> | * '''Simulation Models:''' <code>model.spice</code> / <code>design_header.ngspice</code> | ||
[[Category:LibreSilicon Verification Reports]] | [[index.php?title=Category:LibreSilicon Verification Reports]] | ||
[[Category:LibrePDK]] | [[index.php?title=Category:LibrePDK]] | ||
[[Category:SG13G2]] | [[index.php?title=Category:SG13G2]] | ||
Revision as of 16:12, 1 September 2026
LibrePDK Padframe SPICE Verification Report
Technology: IHP SG13G2 (130nm BiCMOS)
Operating Voltage: 1.2 V
Verification Date: 2026-09-01 16:47:40 UTC
Extracted Netlist: padframe.spice (Magic VLSI Hierarchical Extraction)
Executive Summary
| Test Scenario | Target Net / Pad | Measured Values | Design Specification | Status |
|---|---|---|---|---|
| ESD Clamping Transient | PAD_GPIO_0 (ESD Clamps) | Peak Clamped: 2.75 V | < 15.0 V | PASS |
| Digital Output Drive (Write) | gpio_out_0 → PAD_GPIO_0 | Low: 0.00 V, High: 1.15 V | Rail-to-rail driver transition | PASS |
| Digital Input Sensing (Read / Hi-Z) | PAD_GPIO_1 → gpio_in_1 | Pad 0V → 0.00 V, Pad 1.2V → 1.15 V | Pad 0V -> Core > 0.8V, Pad 1.2V -> Core < 0.2V | PASS |
| Pad-to-Pad Dynamic Loopback | PAD_GPIO_0 → PAD_GPIO_1 | Rx: 0.00V / 1.15V | Full rail-to-rail dynamic loopback across frame | PASS |
Core Signal & Bonding Pad Interface Mapping
The LibrePDK padframe generator exposed unique net names defined in the JSON configuration for seamless Coriolis LEF/DEF digital core integration:
| Subcircuit Port Name | Direction | Interface Type | Associated Physical Layer |
|---|---|---|---|
| VDD | Power Supply | Power / Ground Rail Tap | metal7 / multi-rail |
| VSS | Power Supply | Power / Ground Rail Tap | metal7 / multi-rail |
| gpio_in_0 | Core Output (Pad -> Core) | Core Input Buffer (From Pad) | metal1 |
| gpio_out_0 | Core Input (Core -> Pad) | Core Output Driver (To Pad) | metal1 |
| gpio_en_0 | Core Input (Core -> Pad) | Output Driver Tristate Enable | metal1 |
| PAD_GPIO_0 | Bidirectional / Analog | Bonding Pad (Top Metal) | metal7 |
| gpio_in_1 | Core Output (Pad -> Core) | Core Input Buffer (From Pad) | metal1 |
| gpio_out_1 | Core Input (Core -> Pad) | Core Output Driver (To Pad) | metal1 |
| gpio_en_1 | Core Input (Core -> Pad) | Output Driver Tristate Enable | metal1 |
| PAD_GPIO_1 | Bidirectional / Analog | Bonding Pad (Top Metal) | metal7 |
| spi_miso_in | Core Output (Pad -> Core) | Core Input Buffer (From Pad) | metal1 |
| spi_miso_out | Core Input (Core -> Pad) | Core Output Driver (To Pad) | metal1 |
| spi_miso_en | Core Input (Core -> Pad) | Output Driver Tristate Enable | metal1 |
| PAD_SPI_MISO | Bidirectional / Analog | Bonding Pad (Top Metal) | metal7 |
| spi_cs_in | Core Output (Pad -> Core) | Core Input Buffer (From Pad) | metal1 |
| spi_cs_out | Core Input (Core -> Pad) | Core Output Driver (To Pad) | metal1 |
| spi_cs_en | Core Input (Core -> Pad) | Output Driver Tristate Enable | metal1 |
| PAD_SPI_CS | Bidirectional / Analog | Bonding Pad (Top Metal) | metal7 |
| uart_tx_in | Core Output (Pad -> Core) | Core Input Buffer (From Pad) | metal1 |
| uart_tx_out | Core Input (Core -> Pad) | Core Output Driver (To Pad) | metal1 |
| uart_tx_en | Core Input (Core -> Pad) | Output Driver Tristate Enable | metal1 |
| PAD_UART_TX | Bidirectional / Analog | Bonding Pad (Top Metal) | metal7 |
| uart_rx_in | Core Output (Pad -> Core) | Core Input Buffer (From Pad) | metal1 |
| uart_rx_out | Core Input (Core -> Pad) | Core Output Driver (To Pad) | metal1 |
| uart_rx_en | Core Input (Core -> Pad) | Output Driver Tristate Enable | metal1 |
| PAD_UART_RX | Bidirectional / Analog | Bonding Pad (Top Metal) | metal7 |
| spi_sclk_in | Core Output (Pad -> Core) | Core Input Buffer (From Pad) | metal1 |
| spi_sclk_out | Core Input (Core -> Pad) | Core Output Driver (To Pad) | metal1 |
| spi_sclk_en | Core Input (Core -> Pad) | Output Driver Tristate Enable | metal1 |
| PAD_SPI_SCLK | Bidirectional / Analog | Bonding Pad (Top Metal) | metal7 |
| spi_mosi_in | Core Output (Pad -> Core) | Core Input Buffer (From Pad) | metal1 |
| spi_mosi_out | Core Input (Core -> Pad) | Core Output Driver (To Pad) | metal1 |
| spi_mosi_en | Core Input (Core -> Pad) | Output Driver Tristate Enable | metal1 |
| PAD_SPI_MOSI | Bidirectional / Analog | Bonding Pad (Top Metal) | metal7 |
Transient Simulation Waveforms
1. ESD Clamping Event
Transient simulation applying a 2kV / 1.33A peak Human Body Model (HBM) current pulse directly to the bonding pad:
2. Digital Output Drive (Write)
Driving output data from the digital core logic through the pad cell driver transistors onto the external bonding pad:
3. Digital Input Sensing (Read / Hi-Z)
External signal applied to the bonding pad in tristate / Hi-Z mode, sensed by the internal core input buffer:
4. Full Dynamic Loopback
End-to-end signal transmission across the entire chip: Core Transmitter (Pad A) drives the shared bonding wire bus, sensed by Core Receiver (Pad B):
Physical Verification & GDS Delivery
- GDSII Top Level:
padframe.raw.gds/padframe.gds - Magic Layout:
padframe.mag - SPICE Extracted Netlist:
padframe.spice - Simulation Models:
model.spice/design_header.ngspice
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