Highway: Difference between revisions
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Created page with "Highway is the LibreSilicon VLSI project manager which helps you easily manage multiple Verilog and HDL projects, add them to a die, configure a padframe and run a complete synthesis flow using LibrePDK and Coriolis. Simply create a Python 3.12 environment and install the tool with pip<syntaxhighlight lang="bash"> python3.12 -m venv venv . venv/bin/activate pip install git+https://gitlab.libresilicon.com/leviathan/highway </syntaxhighlight>" |
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Highway is the LibreSilicon VLSI project manager which helps you easily manage multiple Verilog and HDL projects, add them to a die, configure a padframe and run a complete synthesis flow using LibrePDK and Coriolis. | Highway is the LibreSilicon VLSI project manager which helps you easily manage multiple Verilog and HDL projects, add them to a die, configure a padframe and run a complete synthesis flow using [[LibrePDK]] and [https://coriolis.lip6.fr Coriolis]. | ||
Simply create a Python 3.12 environment and install the tool with pip<syntaxhighlight lang="bash"> | Simply create a Python 3.12 environment and install the tool with pip<syntaxhighlight lang="bash"> | ||
Revision as of 00:00, 26 October 2026
Highway is the LibreSilicon VLSI project manager which helps you easily manage multiple Verilog and HDL projects, add them to a die, configure a padframe and run a complete synthesis flow using LibrePDK and Coriolis.
Simply create a Python 3.12 environment and install the tool with pip
python3.12 -m venv venv
. venv/bin/activate
pip install git+https://gitlab.libresilicon.com/leviathan/highway