LibreStandardCell

You need standard logic cells, small logic gate layouts made from place and routing discrete FETs, in order to turn the RTL level logic Yosys spits out into an actual digital chip layout.

You can now use the LibreStandardCell generator and generate custom standard logic cell libraries where you decide the target technology, voltage, height and thermal budget.

Getting the Code

Clone the repository where the JSON files for the cell catalog are constantly updated

git clone https://gitlab.libresilicon.com/leviathan/librestandardcells.git
cd librestandardcells

Docker

We use Docker images for shipping the software in order to make sure that you can avoid all the headaches with dependencies and can go straight to using our tools without friction.

Fetching the Docker image

First pull the docker image in order to make sure that it's up to date, new and updated images are pushed all the time in order to fix new bugs

docker pull leviathanch/librestandardcells:latest

Launch the Docker container

In order to use the interface use the following command here, which binds our local cells_json from the repository into the Docker container

docker run --rm  -p 127.0.0.1:8000:8000 -v $(pwd)/work:/app/work -v $(pwd)/exports:/app/exports -v $(pwd)/cells_json:/app/cells_json leviathanch/librestandardcells:latest

You should end up seeing a message like this on your terminal as soon as the service is started up

Following the link and opening http://0.0.0.0:8000 should then land you on such an interface, where you can select what technology and voltage you wanna generate cells for.

You can either have it dynamically decide on the height of the cells or you can set a fixed height and select multiple cells for batch processing, which is needed for creating a library in which all cells have the same height.

You can also click onto the name of an individual cell which has passed through P&R and the characterization and look at the results as shown below.