High-Speed Impedance-Compensated Pad Cell

High-Speed Impedance-Compensated Pad Cell Architecture & Specification

Document Status: Draft / Initial Specification

Target Process: LibrePDK (IHP SG13G2 / Generic CMOS)

Target Applications: High-Speed Interfaces (DDR4 SSTL/POD, PCIe Gen 1–3, High-Speed GPIO)

1. Overview & Problem Statement

Standard single-stage push-pull digital I/O drivers (consisting of a single large PMOS and NMOS transistor pair) are strictly insufficient for high-speed transmission lines ( single-ended or differential).

Uncompensated drivers suffer from severe non-linearities:

Impedance Mismatch & Reflections: Driver output impedance varies drastically across Process, Voltage, and Temperature (PVT) corners. Unmatched termination causes destructive signal reflections, ringing, and inter-symbol interference (ISI).

Lack of Dynamic Termination: Receiver modes require active On-Die Termination (ODT) to absorb incoming wave fronts without requiring discrete PCB resistors.

Lack of Drive-Strength Control: Variable trace lengths on PCBs require programmable output impedance to match line characteristics (, , , , , ).

To resolve these physical limitations, the next-generation LibreSilicon I/O library must move from static digital drivers to Segmented, PVT-Calibrated Output Drivers with Integrated ODT.

2. Core Architectural Pillars

An impedance-compensated pad cell consists of three mandatory functional subsystems:

High-Level Block Diagram of Calibrated Pad Cell Subsystem

2.1 Multi-Leg / Segmented Output Driver

Rather than a single monolithic transistor, the output driver array is divided into parallel driver legs (typically to ).

Each leg consists of a pull-up PMOS and pull-down NMOS in series with a precision poly-silicon resistor ().

Leg parameters are sized such that the total leg resistance satisfies:

Enabling combinations of parallel legs provides discrete target output impedances:

Output Impedance Selection ()

Enabled Legs ()	Effective Driver Impedance ()	Application Target
1		High-impedance termination leg / Low-power drive
2		ODT Receiver Mode (DDR4 half-strength)
4		Standard PCB Line Match
5		DDR4 Nominal Output Impedance
7		High-drive / PCIe Nominal Output

2.2 On-Die Termination (ODT) Logic

When operating as a receiver, the driver logic overrides normal push-pull operation. The pre-driver controls enable both the PMOS pull-up and NMOS pull-down legs simultaneously to form a center-tapped Thevenin equivalent termination or pull-up termination (e.g., POD12 for DDR4) matched to the trace impedance .

2.3 ZQ Calibration Engine (PVT Compensation)

Because silicon fabrication tolerances, operating temperature, and fluctuations alter and by up to , dynamic digital calibration is required:

An external precision resistor () is tied to a dedicated ZQ Pad.

An internal state machine (using an analog comparator and SAR or Up/Down counter) adjusts binary weighted calibration vectors (CAL_PCODE[N:0] and CAL_NCODE[N:0]).

The calibrated code vectors are distributed to all I/O pads across the die to trim active slice widths continuously.

3. Pre-Driver & Driver Netlist Topology (JSON)

To support automated Place & Route (PnR) inside LibreSilicon, the single-channel gate output format must be refactored into a segmented pre-driver slice array (driver_logic_segmented).

{
	"name": "driver_logic_segmented",
	"nets": [
		"VDD",
		"VSS",
		"IN",
		"EN",
		"OUT",
		"FET_IN",
		"ODT_EN",
		"CAL_PCODE[0]", "CAL_PCODE[1]", "CAL_PCODE[2]", "CAL_PCODE[3]",
		"CAL_NCODE[0]", "CAL_NCODE[1]", "CAL_NCODE[2]", "CAL_NCODE[3]",
		"PMOS_OUT[0]", "PMOS_OUT[1]", "PMOS_OUT[2]", "PMOS_OUT[3]",
		"NMOS_OUT[0]", "NMOS_OUT[1]", "NMOS_OUT[2]", "NMOS_OUT[3]"
	],
	"instances": {
		"M_RX_P": {
			"type": "pmos",
			"nets": { "drain": "IN", "gate": "FET_IN", "source": "VDD", "bulk": "VDD" },
			"current_multiplier": 1.0
		},
		"M_RX_N": {
			"type": "nmos",
			"nets": { "drain": "IN", "gate": "FET_IN", "source": "VSS", "bulk": "VSS" },
			"current_multiplier": 1.0
		},
		"LEG_0_PREDRV": {
			"type": "predriver_slice",
			"nets": {
				"VDD": "VDD",
				"VSS": "VSS",
				"DATA_IN": "OUT",
				"GLOBAL_EN": "EN",
				"ODT_EN": "ODT_EN",
				"BIT_CAL_P": "CAL_PCODE[0]",
				"BIT_CAL_N": "CAL_NCODE[0]",
				"GATE_P": "PMOS_OUT[0]",
				"GATE_N": "NMOS_OUT[0]"
			}
		},
		"LEG_1_PREDRV": {
			"type": "predriver_slice",
			"nets": {
				"VDD": "VDD",
				"VSS": "VSS",
				"DATA_IN": "OUT",
				"GLOBAL_EN": "EN",
				"ODT_EN": "ODT_EN",
				"BIT_CAL_P": "CAL_PCODE[1]",
				"BIT_CAL_N": "CAL_NCODE[1]",
				"GATE_P": "PMOS_OUT[1]",
				"GATE_N": "NMOS_OUT[1]"
			}
		},
		"LEG_2_PREDRV": {
			"type": "predriver_slice",
			"nets": {
				"VDD": "VDD",
				"VSS": "VSS",
				"DATA_IN": "OUT",
				"GLOBAL_EN": "EN",
				"ODT_EN": "ODT_EN",
				"BIT_CAL_P": "CAL_PCODE[2]",
				"BIT_CAL_N": "CAL_NCODE[2]",
				"GATE_P": "PMOS_OUT[2]",
				"GATE_N": "NMOS_OUT[2]"
			}
		},
		"LEG_3_PREDRV": {
			"type": "predriver_slice",
			"nets": {
				"VDD": "VDD",
				"VSS": "VSS",
				"DATA_IN": "OUT",
				"GLOBAL_EN": "EN",
				"ODT_EN": "ODT_EN",
				"BIT_CAL_P": "CAL_PCODE[3]",
				"BIT_CAL_N": "CAL_NCODE[3]",
				"GATE_P": "PMOS_OUT[3]",
				"GATE_N": "NMOS_OUT[3]"
			}
		}
	},
	"inputs": [
		"OUT",
		"EN",
		"ODT_EN",
		"FET_IN",
		"CAL_PCODE[0]", "CAL_PCODE[1]", "CAL_PCODE[2]", "CAL_PCODE[3]",
		"CAL_NCODE[0]", "CAL_NCODE[1]", "CAL_NCODE[2]", "CAL_NCODE[3]"
	],
	"outputs": [
		"IN",
		"PMOS_OUT[0]", "PMOS_OUT[1]", "PMOS_OUT[2]", "PMOS_OUT[3]",
		"NMOS_OUT[0]", "NMOS_OUT[1]", "NMOS_OUT[2]", "NMOS_OUT[3]"
	],
	"pnr_params": {
		"max_signal_metal": 3,
		"y_corridor_tracks": 4,
		"io_buffer_tracks": 2,
		"rail_h": 1.2,
		"num_rows": 4,
		"pin_sides": {
			"PMOS_OUT[0]": "top", "PMOS_OUT[1]": "top", "PMOS_OUT[2]": "top", "PMOS_OUT[3]": "top",
			"NMOS_OUT[0]": "top", "NMOS_OUT[1]": "top", "NMOS_OUT[2]": "top", "NMOS_OUT[3]": "top",
			"FET_IN": "top",
			"EN": "bottom",
			"ODT_EN": "bottom",
			"OUT": "bottom",
			"IN": "bottom",
			"CAL_PCODE[0]": "left", "CAL_PCODE[1]": "left", "CAL_PCODE[2]": "left", "CAL_PCODE[3]": "left",
			"CAL_NCODE[0]": "right", "CAL_NCODE[1]": "right", "CAL_NCODE[2]": "right", "CAL_NCODE[3]": "right"
		}
	}
}

4. LibrePDK Physical Layout & Silicon Process Rules

When laying out the physical pad cell in LibrePDK, engineers must adhere to four strict silicon process guidelines:

4.1 Integrated Poly Resistors

Do NOT rely exclusively on transistor channel resistance for matching. Transistor channel resistance is non-linear with respect to drain-source voltage .

Place STI-isolated poly resistors in series with transistor drains to linearize the driver output impedance curve. Ensure consumes to of total leg impedance ( poly resistor + FET ).

4.2 Metal Routing Congestion & Layer Budget

Metal Layer Allocation: Simple digital pads use and . Segmented drivers routing 8–16 gate signals (PMOS_OUT[N], NMOS_OUT[N]) and calibration control buses MUST utilize (and where available).

Set "max_signal_metal": 3 in PnR configurations to prevent shorting routing tracks across standard cells.

4.3 Slew Rate Mismatch & Skew Control

Asymmetrical routing from the pre-driver data input OUT to individual leg slices creates switching skew between driver branches.

Inter-leg skew induces severe dynamic impedance transients and timing jitter during high-speed signal transitions.

Requirement: The Place & Route engine must enforce symmetric -tree routing for signal paths into LEG_0_PREDRV through LEG_N_PREDRV.

4.4 Pad Capacitance () and ESD Constraints

Paralleling multiple driver transistors increases total junction capacitance on the output pad pin.

Excessive degrades high-frequency edge rates.

Ensure pad layout uses multi-finger folded transitors placed in close proximity to ESD diodes to minimize parasitic substrate capacitance.

5. Implementation Roadmap for LibreSilicon Team

Step 1: Standardize predriver_slice Sub-Macro

Design and simulate the NOR/NAND gating matrix for a single pre-driver slice with ODT enable override.

Step 2: Poly Resistor Characterization

Extract exact sheet resistance () for poly silicon layer in IHP SG13G2 / LibrePDK to dimension the base leg.

Step 3: ZQ Calibration State Machine Netlist

Construct a centralized ZQ controller cell to generate CAL_PCODE and CAL_NCODE vectors across the IO ring.

Step 4: SPICE Corner Analysis

Run transient SPICE simulations across TT, FF, and SS process corners to verify output impedance holding tolerance within of target .