LibreSilicon 1µm CMOS Process Flow (HKUST NFF)

From LibreSilicon
Revision as of 13:26, 26 September 2025 by Leviathan (talk | contribs)
Jump to navigation Jump to search

LibreSilicon 1µm CMOS Process Flow (HKUST NFF)

This document outlines the 1µm CMOS manufacturing process designed for the Hong Kong University of Science and Technology (HKUST) Nanoelectronics Fabrication Facility (NFF). It is a gate-first process utilizing polysilicon for the gate electrode and a shallow trench isolation (STI) approach for device isolation.

The process is designed for manufacturing the LibreSilicon standard logic cells and is licensed under the Libre Silicon public license.

General Manufacturing Steps

The entire fabrication process consists of a sequence of fundamental steps that are repeated in various combinations to build the device layers. The core steps include:

  • Cleaning: Wafers are rigorously cleaned at the beginning of and between major processing stages to remove any particulate or chemical contaminants that could cause defects. This typically involves wet chemical baths (e.g., Sulfuric Peroxide Mix - SPM) and rinsing with deionized water.
  • Photolithography: This is the process of transferring a pattern from a photomask to the wafer surface.
      1. Coating: A light-sensitive material called photoresist is evenly applied to the wafer surface.
      2. Exposure: The wafer is exposed to UV light through a photomask containing the desired pattern. The light alters the chemical structure of the photoresist.
      3. Development: A developer solution is used to remove either the exposed or unexposed portions of the photoresist, leaving the desired pattern on the wafer.
  • Etching: Material is selectively removed from the wafer. This can be done through:
      1. Dry Etching: Using plasmas or reactive gases to remove material (e.g., Reactive Ion Etching - RIE). This method is anisotropic, meaning it etches vertically, creating well-defined features.
      2. Wet Etching: Using liquid chemicals to remove material. This is often isotropic, etching in all directions.
  • Deposition: Thin films of various materials (insulators, conductors, semiconductors) are deposited onto the wafer. Common methods include:
      1. Chemical Vapor Deposition (CVD): A chemical process that deposits a thin film from a vapor or gas state (e.g., LPCVD for silicon nitride or LTO).
      2. Sputtering: A physical vapor deposition method where atoms are ejected from a target material and deposited onto the wafer, commonly used for metals.
  • Ion Implantation: Dopant ions (like Boron for p-type or Phosphorus for n-type) are accelerated and embedded into the silicon substrate to precisely control its electrical properties. The patterned photoresist acts as a mask, blocking ions from certain areas.
  • Thermal Processing (Annealing/Oxidation): The wafer is heated in a furnace for several reasons:
      1. Drive-in/Annealing: To activate the implanted dopants and repair any crystal lattice damage caused by implantation.
      2. Oxidation: To grow a high-quality layer of silicon dioxide (SiO₂) on the silicon surface, which is used for insulation and as a gate dielectric.
  • Chemical Mechanical Planarization (CMP): This process uses a chemical slurry and mechanical polishing to flatten the wafer surface after deposition steps. A flat surface is crucial for the accuracy of subsequent photolithography steps.

Process Flowchart

The overall manufacturing process is a sequence of layering, patterning, and doping steps. Below is the TikZ code for generating a graphical flowchart. (Note: Requires a MediaWiki extension capable of rendering TikZ.) 

\begin{tikzpicture}[node distance=0.7cm, auto]
% Define block styles
\tikzstyle{startstop} = [rectangle, rounded corners, minimum width=4cm, minimum height=1cm, text centered, draw=black, fill=green!30]
\tikzstyle{process} = [rectangle, minimum width=4cm, text width=6cm, minimum height=1cm, text centered, draw=black, fill=blue!20]
\tikzstyle{arrow} = [thick,->,>=stealth]

% Place nodes
\node (start) [startstop] {'''Wafer Start''' (P-type Silicon Substrate)};
\node (step1) [process, below=of start] {'''1. Initial Alignment''' (Mask: ''basic'')};
\node (step2) [process, below=of step1] {'''2. Shallow Trench Isolation (STI)''' (Mask: ''sti'')};
\node (step3) [process, below=of step2] {'''3. N-Well Formation''' (Mask: ''nwell'')};
\node (step4) [process, below=of step3] {'''4. P-Well Formation''' (Mask: ''pwell'')};
\node (step5) [process, below=of step4] {'''5. P-Base Implant''' (Mask: ''pbase'')};
\node (step6) [process, below=of step5] {'''6. N-Base Implant''' (Mask: ''nbase'')};
\node (step7) [process, below=of step6] {'''7. Field Oxide''' (Mask: ''fox'')};
\node (step8) [process, below=of step7] {'''8. SONOS Flash Cell Formation''' (Mask: ''sonos'')};
\node (step9) [process, below=of step8] {'''9. Gate Formation''' (Mask: ''poly'')};
\node (step10) [process, below=of step9] {'''10. Implant Stop Layer''' (Mask: ''implantstop'')};
\node (step11) [process, below=of step10] {'''11. N+ Source/Drain Implant''' (Mask: ''nimplant'')};
\node (step12) [process, below=of step11] {'''12. P+ Source/Drain Implant''' (Mask: ''pimplant'')};
\node (step13) [process, below=of step12] {'''13. Silicidation''' (Mask: ''silicideblock'')};
\node (step14) [process, below=of step13] {'''14. Contact Layer''' (Mask: ''contact'')};
\node (step15) [process, below=of step14] {'''15. Metal 1 Layer''' (Mask: ''metal1'')};
\node (step16) [process, below=of step15] {'''16. Via 1 Layer''' (Mask: ''via1'')};
\node (step17) [process, below=of step16] {'''17. Metal 2 Layer''' (Mask: ''metal2'')};
\node (step18) [process, below=of step17] {'''18. Via 2 Layer''' (Mask: ''via2'')};
\node (step19) [process, below=of step18] {'''19. Metal 3 Layer''' (Mask: ''metal3'')};
\node (step20) [process, below=of step19] {'''20. Passivation (Glass)''' (Mask: ''glass'')};
\node (end) [startstop, below=of step20] {'''Process End'''};

% Draw arrows
\draw [arrow] (start) -- (step1);
\draw [arrow] (step1) -- (step2);
\draw [arrow] (step2) -- (step3);
\draw [arrow] (step3) -- (step4);
\draw [arrow] (step4) -- (step5);
\draw [arrow] (step5) -- (step6);
\draw [arrow] (step6) -- (step7);
\draw [arrow] (step7) -- (step8);
\draw [arrow] (step8) -- (step9);
\draw [arrow] (step9) -- (step10);
\draw [arrow] (step10) -- (step11);
\draw [arrow] (step11) -- (step12);
\draw [arrow] (step12) -- (step13);
\draw [arrow] (step13) -- (step14);
\draw [arrow] (step14) -- (step15);
\draw [arrow] (step15) -- (step16);
\draw [arrow] (step16) -- (step17);
\draw [arrow] (step17) -- (step18);
\draw [arrow] (step18) -- (step19);
\draw [arrow] (step19) -- (step20);
\draw [arrow] (step20) -- (end);

\end{tikzpicture}

Step 1: Initial Alignment

An alignment pattern is etched into the wafer. This initial mask provides reference marks for the stepper to align all subsequent masks accurately.

Step 2: Shallow Trench Isolation (STI)

This step creates electrical isolation between adjacent devices to prevent current leakage. Trenches are etched into the silicon, filled with silicon dioxide (an insulator), and the surface is then flattened using CMP.

Step 3 & 4: N-Well & P-Well Formation

The substrate is selectively doped to create N-wells and P-wells. These wells are the regions where the PMOS and NMOS transistors will be built, respectively. This involves photolithography followed by ion implantation of Phosphorus (for N-well) and Boron (for P-well). The wells are then driven deeper into the substrate through an annealing process.

Step 5 & 6: P-Base & N-Base Formation

These steps involve further implants to create the base regions for Bipolar Junction Transistors (BJTs) that can be integrated alongside the CMOS transistors.

Step 7: Field Oxide (FOX)

A layer of oxide is deposited over regions of the wafer that are not part of the active transistor areas. This thick oxide further isolates devices.

Step 8: SONOS Formation

This sequence of depositions (Silicon-Oxide-Nitride-Oxide-Silicon) creates the gate stack for SONOS non-volatile memory (flash) cells. This step is only performed in the areas where flash cells are desired.

Step 9: Gate Formation

This is a critical step where the transistor gate is formed. A thin, high-quality gate oxide is grown on the active areas, followed by the deposition of polysilicon, which will act as the gate electrode. The polysilicon and gate oxide are then etched using the poly mask to define the gate structures.

Step 10: Implant Stop Layer

An oxide layer is deposited and patterned. This layer protects certain areas of the device during the subsequent source and drain implantation steps.

Step 11 & 12: N+ and P+ Source/Drain Implantation

The source and drain regions for the NMOS and PMOS transistors are created. Using photolithography to protect the other transistor type, the wafer is subjected to a high-dose ion implantation of Phosphorus (for N+) and Boron (for P+). The gate structure itself acts as a mask, ensuring the source and drain are perfectly aligned to the gate (self-aligned process). A final anneal activates these dopants.

Step 13: Silicidation

A layer of metal (Titanium) is deposited and heated. The metal reacts with the exposed silicon on the gate, source, and drain regions to form a metal silicide (Titanium Silicide). This reduces the contact resistance of these regions, improving transistor performance. A blocking mask prevents this formation where it's not wanted (e.g., for polyresistors).

Step 14: Contact Layer

An insulating layer (oxide) is deposited over the entire wafer (Pre-Metal Dielectric or PMD). It is then planarized with CMP. Photolithography and etching are used to create small holes, or "contacts," through the insulator to the silicided gate and source/drain regions below.

Step 15-19: Metallization (Metal 1-3 & Vias 1-2)

This is the "wiring" phase of the chip.

  • Metal Layers: A layer of metal (Aluminum with Nickel barriers) is sputtered over the wafer, filling the contact holes. The metal is then patterned and etched to form the first layer of interconnects (wires).
  • Via Layers: An insulating oxide is deposited and planarized. Vias (similar to contacts) are etched to connect to the metal layer below. The process is then repeated for subsequent metal layers (Metal 2, Metal 3), building up a complex, multi-level wiring structure that connects the millions of transistors on the chip.

Step 20: Passivation (Glass)

A final, thick insulating layer (passivation) is deposited over the entire chip. This layer, typically silicon dioxide or silicon nitride, protects the device from moisture, contamination, and physical damage. The glass mask is used to etch openings over the metal pads, allowing for external connections (wire bonding) to the chip.

Retrieved from "https://wiki.libresilicon.com/index.php?title=LibreSilicon_1µm_CMOS_Process_Flow_(HKUST_NFF)&oldid=561"