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00:1900:19, 26 October 2026 Test Die SG13G2@1.2V (hist | edit) [1,015 bytes] Leviathan (talk | contribs) (Created page with "https://gitlab.libresilicon.com/designs/highwaytestchip/-/tree/sg13g2_1v2?ref_type=heads") Tag: Visual edit

23:5823:58, 25 October 2026 Highway (hist | edit) [750 bytes] Leviathan (talk | contribs) (Created page with "Highway is the LibreSilicon VLSI project manager which helps you easily manage multiple Verilog and HDL projects, add them to a die, configure a padframe and run a complete synthesis flow using LibrePDK and Coriolis. Simply create a Python 3.12 environment and install the tool with pip<syntaxhighlight lang="bash"> python3.12 -m venv venv . venv/bin/activate pip install git+https://gitlab.libresilicon.com/leviathan/highway </syntaxhighlight>") Tag: Visual edit

16:0816:08, 1 September 2026 LibrePDK Padframe SPICE Verification Report GF180A@3.3V (hist | edit) [6,477 bytes] Leviathan (talk | contribs) (Created page with "= LibrePDK Padframe SPICE Verification Report = '''Technology:''' IHP SG13G2 (130nm BiCMOS) '''Operating Voltage:''' 3.3 V '''Verification Date:''' 2026-09-01 16:01:45 UTC '''Extracted Netlist:''' <code>padframe.spice</code> (Magic VLSI Hierarchical Extraction) == Executive Summary == {| class="wikitable" style="text-align:center; width:90%;" ! Test Scenario !! Target Net / Pad !! Measured Values !! Design Specification !! Status |- | style="text-align:left;" |...")
16:0816:08, 1 September 2026 LibrePDK Padframe SPICE Verification Report SG13G2@1.2V (hist | edit) [6,346 bytes] Leviathan (talk | contribs) (Created page with "= LibrePDK Padframe SPICE Verification Report = '''Technology:''' IHP SG13G2 (130nm BiCMOS) '''Operating Voltage:''' 1.2 V '''Verification Date:''' 2026-09-01 16:47:40 UTC '''Extracted Netlist:''' <code>padframe.spice</code> (Magic VLSI Hierarchical Extraction) == Executive Summary == {| class="wikitable" style="text-align:center; width:90%;" ! Test Scenario !! Target Net / Pad !! Measured Values !! Design Specification !! Status |- | style="text-align:left;" |...") Tag: Visual edit: Switched

12:0012:00, 10 August 2026 High-Speed Impedance-Compensated Pad Cell (hist | edit) [8,768 bytes] Leviathan (talk | contribs) (Created page with "= High-Speed Impedance-Compensated Pad Cell Architecture & Specification = '''Document Status:''' Draft / Initial Specification '''Target Process:''' LibrePDK (IHP SG13G2 / Generic CMOS) '''Target Applications:''' High-Speed Interfaces (DDR4 SSTL/POD, PCIe Gen 1–3, High-Speed GPIO) == 1. Overview & Problem Statement == Standard single-stage push-pull digital I/O drivers (consisting of a single large PMOS and NMOS transistor pair) are strictly insufficient for high-spee...") Tag: Visual edit: Switched

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