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Combined display of all available logs of LibreSilicon. You can narrow down the view by selecting a log type, the username (case-sensitive), or the affected page (also case-sensitive).

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  • 23:58, 25 October 2026 Leviathan talk contribs created page Highway (Created page with "Highway is the LibreSilicon VLSI project manager which helps you easily manage multiple Verilog and HDL projects, add them to a die, configure a padframe and run a complete synthesis flow using LibrePDK and Coriolis. Simply create a Python 3.12 environment and install the tool with pip<syntaxhighlight lang="bash"> python3.12 -m venv venv . venv/bin/activate pip install git+https://gitlab.libresilicon.com/leviathan/highway </syntaxhighlight>") Tag: Visual edit