ESD Verification
Below two examples from our automated test suite showcasing how our approach reverse solving the HBM model math as elaborated in Physics-Based_Wire_Sizing_for_I/O_Pad_Cells actually leads to simulation results in ngspice which show that our ESD diodes we chose actually protect our internal circuitry.
Oh wow. When you solve Ohm's law in one direction and then the other, you end up with the current you originally have defined at a certain voltage. Who would have thought this... anyway. Here some examples.
After running
./tests/test_all_padcells.sh visual
you end up with a folder called "generated_output"
We're looking at "generated_output/SG13G2/padcell/1.2V" and "generated_output/SG13G2/padcell/3.3V" here as examples
As described here the test setup is really simple:
The deck models a basic HBM discharge setup with:
- a 100 pF capacitor
- a 1.5 kΩ series resistor
- a switched discharge path
- a bias on
NOT_ENso the driver remains disabled during the pulse
This is just the driver stage test. The input buffer will be having additional tests
The IHP SG13G2 @ 1.2V case
Comparing those two you will notice that the pad with the lower operational voltage needs more area.
While at first counter intuitive, this is because we're not dealing with Ohm's law here but with solid state physics, such as hot carriers and the such.
The thermal budget also plays a role but not as much as electron migration and so.
HBM ESD Dissipation
Assuming a typical ESD discharge of a few nanoseconds the energy absorbed by the chip itself is in the micro Jules range
That's nothing
ESD Waveforms
The current flowing through the pad during an ESD event is only 2100 * 1e-10 at its peak.
2100*0.1nA = 210nA = 0.2uA ... high ohmic inputs when being turned off are doing high ohmic things.
HBM ESD Zoomed In
The IHP SG13G2 @ 3.3V case
When you look at this thing here and its simulation result, it's no surprise that it has the same results as the 1.2V one, because they've been dimensioned based on the same math.
