ESD Verification
Below two examples from our automated test suite showcasing how our approach reverse solving the HBM model math as elaborated in Physics-Based_Wire_Sizing_for_I/O_Pad_Cells actually leads to simulation results in ngspice which show that our ESD diodes we chose actually protect our internal circuitry.
Oh wow. When you solve Ohm's law in one direction and then the other, you end up with the current you originally have defined at a certain voltage. Who would have thought this... anyway. Here some examples.
After running
./tests/test_all_padcells.sh visual
you end up with a folder called "generated_output"
We're looking at "generated_output/SG13G2/padcell/1.2V" and "generated_output/SG13G2/padcell/3.3V" here as examples
As described here the test setup is really simple:
The deck models a basic HBM discharge setup with:
- a 100 pF capacitor
- a 1.5 kΩ series resistor
- a switched discharge path
- a bias on
NOT_ENso the driver remains disabled during the pulse
This is just the driver stage test. The input buffer will be having additional tests
ESD path: Bonding Path to VSS ESD and VDD ESD
The energy which would otherwise go through the internal digital logic takes the alternative path of least resistance, which is the two diodes (we're not generating Schottky diodes yet, see the list of devices in LibrePDK), which we put as close to the bonding pad as possible.
Here a quick drawing to illustrate the configuration.
Inthe case of IHP SG13G2 @ 1.2V the discharge simulation looks like plotted below.
File:Hbm esd dissipation (Diodes) SG13G2@3.3V.pngHbm esd dissipation (Diodes) SG13G2@1.2V
You can see how the voltage on the bonding pad drops while the current and power stays very small
Hbm esd dissipation (Diodes) SG13G2@1.2V
Just as dimensionsed, the ESD protection does its job
ESD path from bonding to internal logic
The second test is the simulation of whether we have a calculated break through between the external bonding pad and the internal GPIO logic going into the digital core logic (center of the die)
As you can see (hopefully) in the drawing I quickly made here in my KolourPaint, we simulate the ESD breakthrough path, which is expected to be neglectable due to our backwards calculation, from the outside pad based on the Human Body Model through the pad cell, through the digital logic to ground.
The IHP SG13G2 @ 1.2V case
Comparing those two you will notice that the pad with the lower operational voltage needs more area.
While at first counter intuitive, this is because we're not dealing with Ohm's law here but with solid state physics, such as hot carriers and the such.
The thermal budget also plays a role but not as much as electron migration and so.
HBM ESD Dissipation
Assuming a typical ESD discharge of a few nanoseconds the energy absorbed by the chip itself is in the micro Jules range
That's nothing
ESD Waveforms
The current flowing through the pad during an ESD event is only 2100 * 1e-10 at its peak.
2100*0.1nA = 210nA = 0.2uA ... high ohmic inputs when being turned off are doing high ohmic things.
