Highway
Highway is the LibreSilicon VLSI project manager which helps you easily manage multiple Verilog and HDL projects, add them to a die, configure a padframe and run a complete synthesis flow using LibrePDK and Coriolis.
Simply create a Python 3.12 environment and install the tool with pip
apt update
apt install g++ git yosys ngspice
python3.12 -m venv venv
. venv/bin/activate
pip install git+https://gitlab.libresilicon.com/leviathan/highway
Test dies
Below a list of links to test die tapeouts for validating the Pad Frame Generator and StdCellLib CellLibraries generator with manufacturing nodes and technologies.