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• 10:21, 30 November 2024 Leviathan talk contribs created page StdCellLib (Created page with "The Standard Cell Library generator has the function of generating a set of logic gates for any given VLSI process node by feeding it the relevant design rules for calculating the dimension and performing the place and route of the relevant transistors, so that a layout can be generated using the synthesis flow provided by [https://github.com/the-openroad-project OpenROAD]. The development of this tool has been mainly funded by NLNet (https://nlnet.nl/project/LibreSilic...") Tag: Visual edit