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Combined display of all available logs of LibreSilicon. You can narrow down the view by selecting a log type, the username (case-sensitive), or the affected page (also case-sensitive).
- 00:19, 26 October 2026 Leviathan talk contribs created page Test Die SG13G2@1.2V (Created page with "https://gitlab.libresilicon.com/designs/highwaytestchip/-/tree/sg13g2_1v2?ref_type=heads") Tag: Visual edit
- 23:58, 25 October 2026 Leviathan talk contribs created page Highway (Created page with "Highway is the LibreSilicon VLSI project manager which helps you easily manage multiple Verilog and HDL projects, add them to a die, configure a padframe and run a complete synthesis flow using LibrePDK and Coriolis. Simply create a Python 3.12 environment and install the tool with pip<syntaxhighlight lang="bash"> python3.12 -m venv venv . venv/bin/activate pip install git+https://gitlab.libresilicon.com/leviathan/highway </syntaxhighlight>") Tag: Visual edit
- 16:38, 1 September 2026 Leviathan talk contribs created page File:Sim 4 pad to pad loopback GF180A@3.3V.png
- 16:38, 1 September 2026 Leviathan talk contribs uploaded File:Sim 4 pad to pad loopback GF180A@3.3V.png
- 16:38, 1 September 2026 Leviathan talk contribs created page File:Sim 3 signal read hiz GF180A@3.3V.png
- 16:38, 1 September 2026 Leviathan talk contribs uploaded File:Sim 3 signal read hiz GF180A@3.3V.png
- 16:37, 1 September 2026 Leviathan talk contribs created page File:Sim 2 signal write GF180A@3.3V.png
- 16:37, 1 September 2026 Leviathan talk contribs uploaded File:Sim 2 signal write GF180A@3.3V.png
- 16:36, 1 September 2026 Leviathan talk contribs created page File:Sim 1 esd clamping GF180A@3.3V.png
- 16:36, 1 September 2026 Leviathan talk contribs uploaded File:Sim 1 esd clamping GF180A@3.3V.png
- 16:14, 1 September 2026 Leviathan talk contribs created page File:Sim 1 esd clamping SG13G2@1.2V.png
- 16:14, 1 September 2026 Leviathan talk contribs uploaded File:Sim 1 esd clamping SG13G2@1.2V.png
- 16:14, 1 September 2026 Leviathan talk contribs created page File:Sim 2 signal write SG13G2@1.2V.png
- 16:14, 1 September 2026 Leviathan talk contribs uploaded File:Sim 2 signal write SG13G2@1.2V.png
- 16:13, 1 September 2026 Leviathan talk contribs created page File:Sim 3 signal read hiz SG13G2@1.2V.png
- 16:13, 1 September 2026 Leviathan talk contribs uploaded File:Sim 3 signal read hiz SG13G2@1.2V.png
- 16:10, 1 September 2026 Leviathan talk contribs created page File:Sim 4 pad to pad loopback SG13G2@1.2V.png
- 16:10, 1 September 2026 Leviathan talk contribs uploaded File:Sim 4 pad to pad loopback SG13G2@1.2V.png
- 16:08, 1 September 2026 Leviathan talk contribs created page LibrePDK Padframe SPICE Verification Report GF180A@3.3V (Created page with "= LibrePDK Padframe SPICE Verification Report = '''Technology:''' IHP SG13G2 (130nm BiCMOS) '''Operating Voltage:''' 3.3 V '''Verification Date:''' 2026-09-01 16:01:45 UTC '''Extracted Netlist:''' <code>padframe.spice</code> (Magic VLSI Hierarchical Extraction) == Executive Summary == {| class="wikitable" style="text-align:center; width:90%;" ! Test Scenario !! Target Net / Pad !! Measured Values !! Design Specification !! Status |- | style="text-align:left;" |...")
- 16:08, 1 September 2026 Leviathan talk contribs created page LibrePDK Padframe SPICE Verification Report SG13G2@1.2V (Created page with "= LibrePDK Padframe SPICE Verification Report = '''Technology:''' IHP SG13G2 (130nm BiCMOS) '''Operating Voltage:''' 1.2 V '''Verification Date:''' 2026-09-01 16:47:40 UTC '''Extracted Netlist:''' <code>padframe.spice</code> (Magic VLSI Hierarchical Extraction) == Executive Summary == {| class="wikitable" style="text-align:center; width:90%;" ! Test Scenario !! Target Net / Pad !! Measured Values !! Design Specification !! Status |- | style="text-align:left;" |...") Tag: Visual edit: Switched
- 08:16, 31 August 2026 Leviathan talk contribs created page File:Sg13g2 1v2 io cell 60mA 1p2V.png
- 08:16, 31 August 2026 Leviathan talk contribs uploaded File:Sg13g2 1v2 io cell 60mA 1p2V.png
- 12:18, 15 August 2026 Leviathan talk contribs created page File:Padframe Example.png
- 12:18, 15 August 2026 Leviathan talk contribs uploaded File:Padframe Example.png
- 21:39, 10 August 2026 Leviathan talk contribs created page File:Predriver slice schematic.png
- 21:39, 10 August 2026 Leviathan talk contribs uploaded File:Predriver slice schematic.png
- 12:04, 10 August 2026 Leviathan talk contribs created page File:Cell Corridor Macro.png
- 12:04, 10 August 2026 Leviathan talk contribs uploaded File:Cell Corridor Macro.png
- 12:00, 10 August 2026 Leviathan talk contribs created page High-Speed Impedance-Compensated Pad Cell (Created page with "= High-Speed Impedance-Compensated Pad Cell Architecture & Specification = '''Document Status:''' Draft / Initial Specification '''Target Process:''' LibrePDK (IHP SG13G2 / Generic CMOS) '''Target Applications:''' High-Speed Interfaces (DDR4 SSTL/POD, PCIe Gen 1–3, High-Speed GPIO) == 1. Overview & Problem Statement == Standard single-stage push-pull digital I/O drivers (consisting of a single large PMOS and NMOS transistor pair) are strictly insufficient for high-spee...") Tag: Visual edit: Switched
- 17:31, 8 August 2026 Leviathan talk contribs created page File:Screeny.png
- 17:31, 8 August 2026 Leviathan talk contribs uploaded File:Screeny.png
- 17:14, 8 August 2026 Leviathan talk contribs created page File:LibreStandardCell screeny2.png
- 17:14, 8 August 2026 Leviathan talk contribs uploaded File:LibreStandardCell screeny2.png
- 17:13, 8 August 2026 Leviathan talk contribs created page LibreStandardCell (Created page with "none|thumb") Tag: Visual edit
- 17:13, 8 August 2026 Leviathan talk contribs created page File:LibreStandardCell screeny1.png
- 17:13, 8 August 2026 Leviathan talk contribs uploaded File:LibreStandardCell screeny1.png
- 12:59, 8 August 2026 Leviathan talk contribs created page File:LibreStandarcCell screeny1.png
- 12:58, 8 August 2026 Leviathan talk contribs uploaded File:LibreStandarcCell screeny1.png
- 14:40, 16 July 2026 Leviathan talk contribs created page High Contrast Resist v1 (Created page with "{| class="wikitable" |'''Component Category''' |'''Specific Chemical''' |'''Function in Matrix''' |'''Weight Percentage (wt%)''' |- |'''Base Polymer Matrix''' |Standard 405nm SLA Resin (e.g., ABS-Like) |Provides acrylate monomers, oligomers, and TPO initiator for radical crosslinking upon exposure. |25.0% - 30.0% |- |'''Primary Solvent''' |PGMEA (1-Methoxy-2-propanol acetate) |Diluent for reducing viscosity to ~10 cP; essential for achieving 1µm spin coating thickness....") Tag: Visual edit
- 13:34, 29 May 2026 Leviathan talk contribs created page File:Forward Hbm esd dissipation.png
- 13:34, 29 May 2026 Leviathan talk contribs uploaded File:Forward Hbm esd dissipation.png
- 13:34, 29 May 2026 Leviathan talk contribs created page File:Reverse Hbm esd dissipation.png
- 13:34, 29 May 2026 Leviathan talk contribs uploaded File:Reverse Hbm esd dissipation.png
- 13:32, 29 May 2026 Leviathan talk contribs created page File:ESD backwards IHP SG13G2-@ 1v2.png
- 13:32, 29 May 2026 Leviathan talk contribs uploaded File:ESD backwards IHP SG13G2-@ 1v2.png
- 13:28, 29 May 2026 Leviathan talk contribs created page File:ESD forward IHP SG13G2 1V2.png
- 13:28, 29 May 2026 Leviathan talk contribs uploaded File:ESD forward IHP SG13G2 1V2.png
- 09:47, 29 May 2026 Leviathan talk contribs created page File:30mA SG13G2@3V3 v2.png
- 09:47, 29 May 2026 Leviathan talk contribs uploaded File:30mA SG13G2@3V3 v2.png
- 09:37, 29 May 2026 Leviathan talk contribs created page File:30mA SG13G2@1V2 v2.png
