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This is the knowledge DB for the [[LibreSilicon stack]] | |||
The official website can be found here under [https://libresilicon.com/ LibreSilicon] | |||
The LibreSilicon knowledge DB is holding [[chemical recipes]] as well as [[software tools]] needed to build free and open source semiconductors. | |||
As well as the [[Danube River]] test wafer, and it's precursor the [[Pearl River]] | |||
The process is flexible and can be implemented with various machines from various vendors. | |||
There's no need to have a very specific machine from a very specific vendor, as long as you're covering the [[Basic Tooling]] you should be ready to go. | |||
The LibrePDK contains tools for generating everything you need in order to generate fully functional chip design based on the design rules you provide and ship the GDS2 file to the factory for manufacturing: | |||
* The Standard Logic Cell generator (https://pdk.libresilicon.com/) | |||
* The Pad Frame Generator which assembles the [[PadCells]] generated based on the design rules and timings provided | |||
https://pdk.libresilicon.com/ | |||
Latest revision as of 08:17, 14 November 2024
This is the knowledge DB for the LibreSilicon stack
The official website can be found here under LibreSilicon
The LibreSilicon knowledge DB is holding chemical recipes as well as software tools needed to build free and open source semiconductors.
As well as the Danube River test wafer, and it's precursor the Pearl River
The process is flexible and can be implemented with various machines from various vendors.
There's no need to have a very specific machine from a very specific vendor, as long as you're covering the Basic Tooling you should be ready to go.
The LibrePDK contains tools for generating everything you need in order to generate fully functional chip design based on the design rules you provide and ship the GDS2 file to the factory for manufacturing:
- The Standard Logic Cell generator (https://pdk.libresilicon.com/)
- The Pad Frame Generator which assembles the PadCells generated based on the design rules and timings provided