Pad Cell Generator: Difference between revisions
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The LibreSilicon Pad Cell Generator is an extension of the [ | [[File:30mA SG13G2@1V2 v2.png|thumb|'''Example 30mA SG13G2@1V2 (version 2)''']] | ||
[[ | The LibreSilicon Pad Cell Generator is an extension of the [[LibrePDK]] and part of the [[Pad Frame Generator]] which besides the driver logic also dynamically generates the mixed signal parts needed for over current and static discharge protection and providing the currents needed for doing useful things with an actual physical chip, like driving an LED or a small motor. | ||
== Types of Pad Cells == | |||
There is the basic [[Pad Cell]] type, as well as the power pad cell. | |||
There is also a very special impedance compensated pad cell in the works ([[High-Speed Impedance-Compensated Pad Cell]]) which is needed in order to hook up DDR4 RAM to our chips or build a PCIe device. | |||
== Existing Groundwork == | == Existing Groundwork == | ||
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Please look at our reference technology folders like the design rule constraints and parameters, for which we introduced a somewhat standardized format with the advent of our [[Danube River]] test wafer generator. | Please look at our reference technology folders like the design rule constraints and parameters, for which we introduced a somewhat standardized format with the advent of our [[Danube River]] test wafer generator. | ||
== Electrical Discharge Protection == | |||
Since we're calculating backwards from the target values we wanna achieve based on values extracted from ngspice simulations using the SPICE models, it is no wonder that the final ngspice simulation turns out to check out fine for all the pad cells we generate. | |||
== | |||
The whole math is being documented in [[Physics-Based Wire Sizing for I/O Pad Cells]] | |||
Subsequently the ngspice analysis and verification of the reverse solved hardware design can be found in [[ESD Verification]] | |||
Latest revision as of 12:47, 10 August 2026
The LibreSilicon Pad Cell Generator is an extension of the LibrePDK and part of the Pad Frame Generator which besides the driver logic also dynamically generates the mixed signal parts needed for over current and static discharge protection and providing the currents needed for doing useful things with an actual physical chip, like driving an LED or a small motor.
Types of Pad Cells
There is the basic Pad Cell type, as well as the power pad cell.
There is also a very special impedance compensated pad cell in the works (High-Speed Impedance-Compensated Pad Cell) which is needed in order to hook up DDR4 RAM to our chips or build a PCIe device.
Existing Groundwork
The generator is based on the work of several folks who started developing puzzle pieces for it before Google ran out of funding internally and the project had to go on hiatus
Here's some works our generator will be based on:
- Gowthami Nalla did some work with the logic circuit and the driver but it's specific to XFAB only; https://github.com/gowthaminalla/bidirectional-buffer/
- Very rudimentary development has been done on the ESD front: https://github.com/AishikAnalogCKTdesign/ESD
- Philip's pad frame generator (Perl): https://www2.futureware.at/~philipp/vsd2018/
- Philip's very basic Perl based pad cell generator (https://pdk.libresilicon.com/PadCellGenerator.zip)
- Perl based
- Not portable
- Needs smarter ESD protection
- Needs smarter IO config
- Doesn't have termination resistor configuration (needed for DDR3/DDR4 PHYs)
- Not even yet half finished
Configuration
The Pad Cell Generator has the task of generating a Pad Cell for generating a pad frame for taping out a circuit with any given set of design rules for any given process.
Just as with the Standard Cell Generator, you need to provide the Pad Cell Generator the appropriate configuration telling it about all the design constraints and mixed signal characteristics of the process you are targeting.
Please look at our reference technology folders like the design rule constraints and parameters, for which we introduced a somewhat standardized format with the advent of our Danube River test wafer generator.
Electrical Discharge Protection
Since we're calculating backwards from the target values we wanna achieve based on values extracted from ngspice simulations using the SPICE models, it is no wonder that the final ngspice simulation turns out to check out fine for all the pad cells we generate.
The whole math is being documented in Physics-Based Wire Sizing for I/O Pad Cells
Subsequently the ngspice analysis and verification of the reverse solved hardware design can be found in ESD Verification