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Sim 4 pad to pad loopback GF180A@3.3V.png Leviathan
16:38, 1 September 2026
1,500 × 750; 119 KB
Sim 3 signal read hiz GF180A@3.3V.png Leviathan
16:38, 1 September 2026
1,500 × 750; 71 KB
Sim 2 signal write GF180A@3.3V.png Leviathan
16:37, 1 September 2026
1,500 × 750; 77 KB
Sim 1 esd clamping GF180A@3.3V.png Leviathan
16:36, 1 September 2026
1,500 × 750; 72 KB
Sim 1 esd clamping SG13G2@1.2V.png Leviathan
16:14, 1 September 2026
1,500 × 750; 76 KB
Sim 2 signal write SG13G2@1.2V.png Leviathan
16:14, 1 September 2026
1,500 × 750; 71 KB
Sim 3 signal read hiz SG13G2@1.2V.png Leviathan
16:13, 1 September 2026
1,500 × 750; 68 KB
Sim 4 pad to pad loopback SG13G2@1.2V.png Leviathan
16:10, 1 September 2026
1,500 × 750; 111 KB
Sg13g2 1v2 io cell 60mA 1p2V.png Leviathan
08:16, 31 August 2026
196 × 1,003; 52 KB
Padframe Example.png Leviathan
12:18, 15 August 2026
1,002 × 1,001; 181 KB
Predriver slice schematic.png Leviathan
21:39, 10 August 2026
3,780 × 895; 127 KB
Cell Corridor Macro.png Leviathan
12:04, 10 August 2026
1,024 × 559; 367 KB
Screeny.png Leviathan
17:31, 8 August 2026
951 × 141; 30 KB
LibreStandardCell screeny2.png Leviathan
17:14, 8 August 2026
1,311 × 895; 179 KB
LibreStandardCell screeny1.png Leviathan
17:13, 8 August 2026
1,406 × 937; 193 KB
LibreStandarcCell screeny1.png Leviathan
12:58, 8 August 2026
1,401 × 947; 195 KB
Forward Hbm esd dissipation.png Leviathan
13:34, 29 May 2026
1,920 × 960; 123 KB
Reverse Hbm esd dissipation.png Leviathan
13:34, 29 May 2026
1,920 × 960; 123 KB
ESD backwards IHP SG13G2-@ 1v2.png Leviathan
13:32, 29 May 2026
435 × 967; 160 KB
ESD forward IHP SG13G2 1V2.png Leviathan
13:28, 29 May 2026
483 × 960; 155 KB
30mA SG13G2@3V3 v2.png Leviathan
09:47, 29 May 2026
397 × 839; 66 KB
30mA SG13G2@1V2 v2.png Leviathan
09:37, 29 May 2026
357 × 932; 71 KB
Pad Frame v2 Example SG13G2@1V2.png Leviathan
09:27, 29 May 2026
927 × 856; 95 KB
HBM ESD dissipation SG13G2@1.2V.png Leviathan
00:42, 28 May 2026
1,920 × 960; 75 KB
Hbm esd waveforms.png Leviathan
00:17, 28 May 2026
1,920 × 960; 92 KB
PAD-VDD-VSS ESD path.png Leviathan
23:44, 27 May 2026
281 × 442; 11 KB
ESD path from outside to internal.png Leviathan
19:15, 26 May 2026
578 × 358; 11 KB
Io cell 20mA@1.2V.png Leviathan
01:42, 26 May 2026
1,024 × 768; 78 KB
Diode Example.png Leviathan
01:13, 26 May 2026
1,024 × 768; 87 KB
Single Gate Example.png Leviathan
01:10, 26 May 2026
1,024 × 768; 31 KB
Fingered Transistor.png Leviathan
01:07, 26 May 2026
1,024 × 768; 77 KB
Strip Resistor Example.png Leviathan
00:34, 26 May 2026
1,024 × 768; 38 KB
LibrePDK Meander Example.png Leviathan
00:23, 26 May 2026
1,024 × 768; 50 KB
50pF MiMCap (GF180A, 3.3V).png Leviathan
00:19, 26 May 2026
1,024 × 768; 88 KB
Io cell 20mA.png Leviathan
22:55, 25 May 2026
1,024 × 768; 90 KB
Preliminary First Pad Frame generated.png Leviathan
21:53, 25 May 2026
900 × 891; 70 KB
LS1U flow.png Leviathan
16:20, 6 November 2025
390 × 2,373; 158 KB
My image 1.png Leviathan
14:48, 26 September 2025
848 × 5,203; 206 KB
Transmission gate.png Leviathan
19:12, 21 September 2025
536 × 409; 14 KB
Output Driver.png Leviathan
20:19, 20 September 2025
966 × 613; 27 KB
Inverter.png Leviathan
19:51, 20 September 2025
1,920 × 692; 61 KB
NAND2 Gate.png Leviathan
19:30, 20 September 2025
1,920 × 800; 58 KB
Pad Cell Schematics.png Leviathan
16:59, 20 September 2025
1,037 × 615; 75 KB
LibrePDK.png Leviathan
13:37, 19 July 2025
950 × 618; 94 KB
Closeup FETs.png Leviathan
07:09, 14 July 2025
979 × 864; 67 KB
Transistor Structures.png Leviathan
06:57, 14 July 2025
967 × 347; 16 KB
Large Meander Resistors.png Leviathan
06:56, 14 July 2025
1,126 × 672; 47 KB
Small Meander Resistors.png Leviathan
06:54, 14 July 2025
1,211 × 412; 26 KB
Strip resistors.png Leviathan
06:52, 14 July 2025
964 × 504; 22 KB
Danube For Existing Foundry.png Leviathan
19:27, 2 December 2024
1,174 × 509; 221 KB

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