User contributions for Leviathan

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A user with 550 edits. Account created on 20 August 2021.

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02:5002:50, 24 November 2025 diff hist +206 Danube River →Successful tapeouts current Tag: Visual edit

16:2116:21, 6 November 2025 diff hist +32 LibreSilicon 1µm CMOS Process Flow (HKUST NFF) Integrated TikZ renderer is broken in newest MediaWiki current Tag: Visual edit
16:2016:20, 6 November 2025 diff hist +17 N File:LS1U flow.png No edit summary current
16:1316:13, 6 November 2025 diff hist −3,484 LibreSilicon 1µm CMOS Process Flow (HKUST NFF) No edit summary

16:0716:07, 12 October 2025 diff hist −24 Main Page No edit summary current Tag: Visual edit
16:0716:07, 12 October 2025 diff hist +24 Main Page No edit summary Tag: Visual edit
16:0516:05, 12 October 2025 diff hist +24,015 N Expert Assessment on Bulk Contact Geometry for Multi-Fingered MOSFET P-Cells in LibrePDK Created page with " == I. Introduction and Fundamental Role of the Bulk Terminal == The design of robust parameterized cells (P-cells) for integrated circuit development, particularly for wide, multi-fingered Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), hinges critically on controlling parasitic elements. Multi-fingered transistors are a common architectural choice in modern very large scale integration (VLSI) design, used primarily to achieve high current driving capabili..." current Tag: Visual edit
16:0516:05, 12 October 2025 diff hist +4 Fingered Transistors No edit summary current Tag: Visual edit
16:0416:04, 12 October 2025 diff hist +99 Fingered Transistors No edit summary Tag: Visual edit
16:0416:04, 12 October 2025 diff hist +5,577 N Analysis: Single Bulk Contact vs. Bulk Contact Ring for a FET Created page with "This document analyzes the trade-offs between using a single, small bulk contact versus a continuous bulk contact ring (guard ring) around a Field-Effect Transistor (FET). The choice significantly impacts area, performance, and reliability. === Key Concepts === * '''Bulk (or Body):''' The underlying silicon substrate on which the transistor is built. It must be tied to a stable voltage potential (e.g., VSS for NMOS, VDD for PMOS). * '''Bulk Contact:''' The physical con..." current Tag: Visual edit
16:0316:03, 12 October 2025 diff hist +243 Fingered Transistors No edit summary Tag: Visual edit
16:0016:00, 12 October 2025 diff hist +45 Pad Cell →Transmission gate current Tag: Visual edit
15:5815:58, 12 October 2025 diff hist +34 Main Page No edit summary Tag: Visual edit

14:5814:58, 26 September 2025 diff hist −107 LibreSilicon 1µm CMOS Process Flow (HKUST NFF) →Process Flowchart Tag: Visual edit
14:4814:48, 26 September 2025 diff hist −25 LibreSilicon 1µm CMOS Process Flow (HKUST NFF) →Process Flowchart Tag: Manual revert
14:4814:48, 26 September 2025 diff hist +3,562 N File:My image 1.png Automatically uploaded by PGFTikZ extension current
14:4414:44, 26 September 2025 diff hist +25 LibreSilicon 1µm CMOS Process Flow (HKUST NFF) →Process Flowchart Tag: Reverted
14:4114:41, 26 September 2025 diff hist +20 LibreSilicon 1µm CMOS Process Flow (HKUST NFF) →Process Flowchart
14:4014:40, 26 September 2025 diff hist −2 LibreSilicon 1µm CMOS Process Flow (HKUST NFF) →Process Flowchart
14:4014:40, 26 September 2025 diff hist −2 LibreSilicon 1µm CMOS Process Flow (HKUST NFF) →Process Flowchart
14:3914:39, 26 September 2025 diff hist −76 LibreSilicon 1µm CMOS Process Flow (HKUST NFF) →Process Flowchart
14:3814:38, 26 September 2025 diff hist +260 LibreSilicon 1µm CMOS Process Flow (HKUST NFF) →Process Flowchart
13:5113:51, 26 September 2025 diff hist −1 LibreSilicon 1µm CMOS Process Flow (HKUST NFF) →Process Flowchart
13:3113:31, 26 September 2025 diff hist +19 LibreSilicon 1µm CMOS Process Flow (HKUST NFF) →Process Flowchart
13:3113:31, 26 September 2025 diff hist +96 LibreSilicon 1µm CMOS Process Flow (HKUST NFF) →Process Flowchart
13:2713:27, 26 September 2025 diff hist +31 LibreSilicon 1µm CMOS Process Flow (HKUST NFF) →Process Flowchart
13:2613:26, 26 September 2025 diff hist +79 LibreSilicon 1µm CMOS Process Flow (HKUST NFF) No edit summary Tag: Visual edit: Switched
13:2513:25, 26 September 2025 diff hist +2,131 LibreSilicon 1µm CMOS Process Flow (HKUST NFF) No edit summary
13:2113:21, 26 September 2025 diff hist +8,679 N LibreSilicon 1µm CMOS Process Flow (HKUST NFF) Created page with "This document outlines the 1µm CMOS manufacturing process designed for the Hong Kong University of Science and Technology (HKUST) Nanoelectronics Fabrication Facility (NFF). It is a '''gate-first''' process utilizing polysilicon for the gate electrode and a shallow trench isolation (STI) approach for device isolation. The process is designed for manufacturing the LibreSilicon standard logic cells and is licensed under the Libre Silicon public license. == General Manuf..." Tag: Visual edit: Switched
13:2013:20, 26 September 2025 diff hist +75 Pearl River No edit summary current Tag: Visual edit

17:0117:01, 25 September 2025 diff hist +28 StdCellLib No edit summary current Tag: Visual edit
17:0017:00, 25 September 2025 diff hist +101 StdCellLib No edit summary Tag: Visual edit

19:1319:13, 21 September 2025 diff hist +70 Pad Cell →Transmission gate Tag: Visual edit
19:1219:12, 21 September 2025 diff hist +28 N File:Transmission gate.png No edit summary current

20:2220:22, 20 September 2025 diff hist +196 Pad Cell →Driver circuit Tag: Visual edit
20:2020:20, 20 September 2025 diff hist +62 Pad Cell →Driver circuit Tag: Visual edit
20:1920:19, 20 September 2025 diff hist +14 N File:Output Driver.png No edit summary current
20:1820:18, 20 September 2025 diff hist +281 Pad Cell →Transmission gate Tag: Visual edit
19:5419:54, 20 September 2025 diff hist +25 Pad Cell No edit summary Tag: Visual edit
19:5319:53, 20 September 2025 diff hist −4 Pad Cell →INV (Inverter)
19:5319:53, 20 September 2025 diff hist +41 Pad Cell →INV (Inverter)
19:5219:52, 20 September 2025 diff hist +251 Pad Cell →INV (Inverter)
19:5119:51, 20 September 2025 diff hist +51 Pad Cell →INV (Inverter) Tag: Visual edit
19:5119:51, 20 September 2025 diff hist +13 N File:Inverter.png No edit summary current
19:4319:43, 20 September 2025 diff hist +123 Pad Cell →NAND2 (NAND gate)
19:4119:41, 20 September 2025 diff hist 0 Pad Cell →NAND2 (NAND gate)
19:4119:41, 20 September 2025 diff hist +41 Pad Cell →Driver Logic
19:3719:37, 20 September 2025 diff hist −1 Pad Cell →NAND2 (NAND gate)
19:3419:34, 20 September 2025 diff hist −1 Pad Cell →NAND2 (NAND gate)
19:3319:33, 20 September 2025 diff hist −4 Pad Cell →INV (Inverter) Tag: Visual edit

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